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https://github.com/c64scene-ar/llvm-6502.git
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ARM: improve RTABI 4.2 conformance on Linux
The set of functions defined in the RTABI was separated for no real reason. This brings us closer to proper utilisation of the functions defined by the RTABI. It also sets the ground for correctly emitting function calls to AEABI functions on all AEABI conforming platforms. The previously existing lie on the behaviour of __ldivmod and __uldivmod is propagated as it is beyond the scope of the change. The changes to the test are due to the fact that we now use the divmod functions which return both the quotient and remainder and thus we no longer need to invoke two functions on Linux (making it closer to EABI's behaviour). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215862 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Saleem Abdulrasool
parent
c5b413060c
commit
f15492fd72
@ -312,8 +312,8 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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// Conversions between floating types.
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// RTABI chapter 4.1.2, Table 7
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{ RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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// Integer to floating-point conversions.
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// RTABI chapter 4.1.2, Table 8
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@ -328,21 +328,31 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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// Long long helper functions
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// RTABI chapter 4.2, Table 9
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{ RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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// FIXME: __aeabi_ldivmod is SDIVREM not SDIV; we should custom lower this
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{ RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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// FIXME: __aeabi_uldivmod is UDIVREM not UDIV; we should custom lower this
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{ RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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// Integer division functions
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// RTABI chapter 4.3.1
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{ RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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{ RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
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// Memory operations
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// RTABI chapter 4.3.4
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@ -357,6 +367,9 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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if (LC.Cond != ISD::SETCC_INVALID)
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setCmpLibcallCC(LC.Op, LC.Cond);
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}
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setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
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setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
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}
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if (Subtarget->isTargetWindows()) {
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@ -676,31 +689,9 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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}
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// FIXME: Also set divmod for SREM on EABI
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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// Register based DivRem for AEABI (RTABI 4.2)
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if (Subtarget->isTargetAEABI()) {
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setLibcallName(RTLIB::SDIVREM_I8, "__aeabi_idivmod");
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setLibcallName(RTLIB::SDIVREM_I16, "__aeabi_idivmod");
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setLibcallName(RTLIB::SDIVREM_I32, "__aeabi_idivmod");
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setLibcallName(RTLIB::SDIVREM_I64, "__aeabi_ldivmod");
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setLibcallName(RTLIB::UDIVREM_I8, "__aeabi_uidivmod");
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setLibcallName(RTLIB::UDIVREM_I16, "__aeabi_uidivmod");
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setLibcallName(RTLIB::UDIVREM_I32, "__aeabi_uidivmod");
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setLibcallName(RTLIB::UDIVREM_I64, "__aeabi_uldivmod");
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setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::ARM_AAPCS);
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setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::ARM_AAPCS);
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setLibcallCallingConv(RTLIB::SDIVREM_I32, CallingConv::ARM_AAPCS);
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setLibcallCallingConv(RTLIB::SDIVREM_I64, CallingConv::ARM_AAPCS);
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setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::ARM_AAPCS);
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setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::ARM_AAPCS);
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setLibcallCallingConv(RTLIB::UDIVREM_I32, CallingConv::ARM_AAPCS);
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setLibcallCallingConv(RTLIB::UDIVREM_I64, CallingConv::ARM_AAPCS);
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setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
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setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
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} else {
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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if (!Subtarget->isTargetAEABI()) {
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setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
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setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
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}
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@ -17,10 +17,7 @@ entry:
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; EABI: __aeabi_idivmod
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; EABI: mov [[div:r[0-9]+]], r0
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; EABI: mov [[rem:r[0-9]+]], r1
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; GNU: __aeabi_idiv
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; GNU: mov [[sum:r[0-9]+]], r0
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; GNU: __modsi3
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; GNU: add [[sum]]{{.*}}r0
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; GNU: __aeabi_idivmod
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; DARWIN: ___divsi3
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; DARWIN: mov [[sum:r[0-9]+]], r0
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; DARWIN: __modsi3
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@ -34,7 +31,7 @@ entry:
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%conv14 = trunc i32 %add13 to i16
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; EABI: add r0{{.*}}r1
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; EABI: sxth r0, r0
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; GNU: add r0{{.*}}[[sum]]
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; GNU: add r0{{.*}}
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; GNU: sxth r0, r0
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; DARWIN: add r0{{.*}}[[sum]]
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; DARWIN: sxth r0, r0
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@ -51,10 +48,7 @@ entry:
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; EABI: __aeabi_idivmod
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; EABI: mov [[div:r[0-9]+]], r0
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; EABI: mov [[rem:r[0-9]+]], r1
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; GNU: __aeabi_idiv
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; GNU: mov [[sum:r[0-9]+]], r0
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; GNU: __modsi3
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; GNU: add [[sum]]{{.*}}r0
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; GNU: __aeabi_idivmod
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; DARWIN: ___divsi3
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; DARWIN: mov [[sum:r[0-9]+]], r0
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; DARWIN: __modsi3
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@ -66,7 +60,7 @@ entry:
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%add = add nsw i32 %rem, %div
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%add2 = add nsw i32 %add, %rem1
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; EABI: add r0{{.*}}r1
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; GNU: add r0{{.*}}[[sum]]
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; GNU: add r0{{.*}}
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; DARWIN: add r0{{.*}}[[sum]]
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ret i32 %add2
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}
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@ -79,10 +73,7 @@ entry:
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%div = udiv i32 %a, %b
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%rem = urem i32 %a, %b
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; EABI: __aeabi_uidivmod
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; GNU: __aeabi_uidiv
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; GNU: mov [[sum:r[0-9]+]], r0
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; GNU: __umodsi3
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; GNU: add [[sum]]{{.*}}r0
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; GNU: __aeabi_uidivmod
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; DARWIN: ___udivsi3
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; DARWIN: mov [[sum:r[0-9]+]], r0
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; DARWIN: __umodsi3
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@ -94,7 +85,7 @@ entry:
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%add = add nuw i32 %rem, %div
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%add2 = add nuw i32 %add, %rem1
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; EABI: add r0{{.*}}r1
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; GNU: add r0{{.*}}[[sum]]
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; GNU: add r0{{.*}}
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; DARWIN: add r0{{.*}}[[sum]]
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ret i32 %add2
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}
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@ -131,15 +122,13 @@ entry:
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%div = sdiv i32 %a, %b
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%rem = srem i32 %a, %b
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; EABI: __aeabi_idivmod
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; GNU: __aeabi_idiv
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; GNU: mov [[sum:r[0-9]+]], r0
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; GNU: __modsi3
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; GNU: __aeabi_idivmod
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; DARWIN: ___divsi3
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; DARWIN: mov [[sum:r[0-9]+]], r0
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; DARWIN: __modsi3
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%add = add nsw i32 %rem, %div
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; EABI: add r0{{.*}}r1
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; GNU: add r0{{.*}}[[sum]]
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; EABI: add r0{{.*}}r1
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; GNU: add r0{{.*}}r1
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; DARWIN: add r0{{.*}}[[sum]]
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ret i32 %add
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}
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