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Use TableGen to emit information for dwarf register numbers.

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This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43997 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
2007-11-11 19:50:10 +00:00
parent af1b61debd
commit f191c80cd7
23 changed files with 932 additions and 876 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
lib/Target/Mips/MipsRegisterInfo.cpp
View File

@@ -538,5 +538,11 @@ getEHHandlerRegister() const {
return 0;
}
int MipsRegisterInfo::
getDwarfRegNum(unsigned RegNum) const {
assert(0 && "What is the dwarf register number");
return -1;
}
#include "MipsGenRegisterInfo.inc"

2
lib/Target/Mips/MipsRegisterInfo.h
View File

@@ -96,6 +96,8 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo {
/// Exception handling queries.
unsigned getEHExceptionRegister() const;
unsigned getEHHandlerRegister() const;
int getDwarfRegNum(unsigned RegNum) const;
};
} // end namespace llvm

64
lib/Target/Mips/MipsRegisterInfo.td
View File

@@ -23,38 +23,38 @@ class MipsGPRReg<bits<5> num, string n> : MipsReg<n> {
}
// CPU GPR Registers
def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<0>;
def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<1>;
def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<2>;
def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<3>;
def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<5>;
def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<5>;
def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<6>;
def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<7>;
def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<8>;
def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<9>;
def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<10>;
def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<11>;
def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<12>;
def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<13>;
def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<14>;
def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<15>;
def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<16>;
def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<17>;
def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<18>;
def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<19>;
def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<20>;
def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<21>;
def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<22>;
def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<23>;
def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<24>;
def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<25>;
def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<26>;
def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<27>;
def GP : MipsGPRReg< 28, "GP">, DwarfRegNum<28>;
def SP : MipsGPRReg< 29, "SP">, DwarfRegNum<29>;
def FP : MipsGPRReg< 30, "FP">, DwarfRegNum<30>;
def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<31>;
def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<[0]>;
def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>;
def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[5]>;
def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>;
def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>;
def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>;
def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>;
def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>;
def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>;
def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>;
def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>;
def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>;
def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>;
def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>;
def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>;
def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>;
def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>;
def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>;
def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>;
def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>;
def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>;
def GP : MipsGPRReg< 28, "GP">, DwarfRegNum<[28]>;
def SP : MipsGPRReg< 29, "SP">, DwarfRegNum<[29]>;
def FP : MipsGPRReg< 30, "FP">, DwarfRegNum<[30]>;
def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<[31]>;
// CPU Registers Class
def CPURegs : RegisterClass<"Mips", [i32], 32,