6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-15 20:29:48 +00:00
Code Issues Projects Releases Wiki Activity

More corrections for flagged copyto/from reg

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24828 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-12-18 15:36:21 +00:00
parent 755dd09815
commit f1a47c3371
1 changed files with 11 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -568,15 +568,17 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
case ISD::CopyFromReg:
Tmp1 = LegalizeOp(Node->getOperand(0));
Result = Op.getValue(0);
if (Node->getNumOperands() == 2) {
if (Node->getNumValues() == 2) {
if (Tmp1 != Node->getOperand(0))
Result = DAG.getCopyFromReg(Tmp1,
cast<RegisterSDNode>(Node->getOperand(1))->getReg(),
Node->getValueType(0));
} else {
assert(Node->getNumOperands() == 3 && "Invalid copyfromreg!");
assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
if (Node->getNumOperands() == 3)
Tmp2 = LegalizeOp(Node->getOperand(2));
if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2))
if (Tmp1 != Node->getOperand(0) ||
(Node->getNumOperands() == 3 && Tmp2 != Node->getOperand(2)))
Result = DAG.getCopyFromReg(Tmp1,
cast<RegisterSDNode>(Node->getOperand(1))->getReg(),
Node->getValueType(0), Tmp2);
@ -1140,15 +1142,16 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
"Register type must be legal!");
// Legalize the incoming value (must be a legal type).
Tmp2 = LegalizeOp(Node->getOperand(2));
if (Node->getNumOperands() == 3) {
if (Node->getNumValues() == 1) {
if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2))
Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1,
Node->getOperand(1), Tmp2);
} else {
assert(Node->getNumOperands() == 4 && "Unknown CopyToReg");
assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
if (Node->getNumOperands() == 4)
Tmp3 = LegalizeOp(Node->getOperand(3));
if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
Tmp3 != Node->getOperand(3)) {
(Node->getNumOperands() == 4 && Tmp3 != Node->getOperand(3))) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
Result = DAG.getCopyToReg(Tmp1, Reg, Tmp2, Tmp3);
}