From f1ae78af1796ec122e3cf75ab4826495eb5a4e8d Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Wed, 27 Jul 2011 20:37:36 +0000 Subject: [PATCH] ARM assembly parsing and encoding tests for TEQ instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136259 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/MC/ARM/basic-arm-instructions.s | 34 ++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index 8232d1d108a..f911aae6263 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -1914,3 +1914,37 @@ _func: @ encoding: [0x72,0x28,0xbf,0xd6] @ CHECK: sxth r9, r3, ror #24 @ encoding: [0x73,0x9c,0xbf,0xe6] + + +@------------------------------------------------------------------------------ +@ FIXME: TBB/TBH +@------------------------------------------------------------------------------ + + +@------------------------------------------------------------------------------ +@ TEQ +@------------------------------------------------------------------------------ + teq r5, #0xf000 + teq r4, r5 + teq r4, r5, lsl #5 + teq r4, r5, lsr #5 + teq r4, r5, lsr #5 + teq r4, r5, asr #5 + teq r4, r5, ror #5 + teq r6, r7, lsl r9 + teq r6, r7, lsr r9 + teq r6, r7, asr r9 + teq r6, r7, ror r9 + +@ CHECK: teq r5, #61440 @ encoding: [0x0f,0x0a,0x35,0xe3] +@ CHECK: teq r4, r5 @ encoding: [0x05,0x00,0x34,0xe1] +@ CHECK: teq r4, r5, lsl #5 @ encoding: [0x85,0x02,0x34,0xe1] +@ CHECK: teq r4, r5, lsr #5 @ encoding: [0xa5,0x02,0x34,0xe1] +@ CHECK: teq r4, r5, lsr #5 @ encoding: [0xa5,0x02,0x34,0xe1] +@ CHECK: teq r4, r5, asr #5 @ encoding: [0xc5,0x02,0x34,0xe1] +@ CHECK: teq r4, r5, ror #5 @ encoding: [0xe5,0x02,0x34,0xe1] +@ CHECK: teq r6, r7, lsl r9 @ encoding: [0x17,0x09,0x36,0xe1] +@ CHECK: teq r6, r7, lsr r9 @ encoding: [0x37,0x09,0x36,0xe1] +@ CHECK: teq r6, r7, asr r9 @ encoding: [0x57,0x09,0x36,0xe1] +@ CHECK: teq r6, r7, ror r9 @ encoding: [0x77,0x09,0x36,0xe1] +