mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-19 17:33:29 +00:00
1. Simplfy bit operations.
2. Coalesce instruction cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29135 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Laskey
parent
262041892d
commit
f1b05bf755
@ -16,64 +16,58 @@
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#include "CodeEmitterGen.h"
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#include "CodeGenTarget.h"
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#include "Record.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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void CodeEmitterGen::emitInstrOpBits(std::ostream &o,
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const std::vector<RecordVal> &Vals,
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std::map<std::string, unsigned> &OpOrder,
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std::map<std::string, bool> &OpContinuous)
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{
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for (unsigned f = 0, e = Vals.size(); f != e; ++f) {
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if (Vals[f].getPrefix()) {
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BitsInit *FieldInitializer = (BitsInit*)Vals[f].getValue();
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void CodeEmitterGen::reverseBits(std::vector<Record*> &Insts) {
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for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
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I != E; ++I) {
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Record *R = *I;
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if (R->getName() == "PHI" || R->getName() == "INLINEASM") continue;
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BitsInit *BI = R->getValueAsBitsInit("Inst");
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// Scan through the field looking for bit initializers of the current
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// variable...
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for (int i = FieldInitializer->getNumBits()-1; i >= 0; --i) {
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Init *I = FieldInitializer->getBit(i);
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if (BitInit *BI = dynamic_cast<BitInit*>(I)) {
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DEBUG(o << " // bit init: f: " << f << ", i: " << i << "\n");
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} else if (UnsetInit *UI = dynamic_cast<UnsetInit*>(I)) {
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DEBUG(o << " // unset init: f: " << f << ", i: " << i << "\n");
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} else if (VarBitInit *VBI = dynamic_cast<VarBitInit*>(I)) {
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TypedInit *TI = VBI->getVariable();
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if (VarInit *VI = dynamic_cast<VarInit*>(TI)) {
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// If the bits of the field are laid out consecutively in the
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// instruction, then instead of separately ORing in bits, just
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// mask and shift the entire field for efficiency.
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if (OpContinuous[VI->getName()]) {
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// already taken care of in the loop above, thus there is no
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// need to individually OR in the bits
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// for debugging, output the regular version anyway, commented
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DEBUG(o << " // Value |= getValueBit(op"
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<< OpOrder[VI->getName()] << ", " << VBI->getBitNum()
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<< ")" << " << " << i << ";\n");
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} else {
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o << " Value |= getValueBit(op" << OpOrder[VI->getName()]
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<< ", " << VBI->getBitNum()
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<< ")" << " << " << i << ";\n";
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}
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} else if (FieldInit *FI = dynamic_cast<FieldInit*>(TI)) {
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// FIXME: implement this!
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std::cerr << "Error: FieldInit not implemented!\n";
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abort();
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} else {
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std::cerr << "Error: unimplemented case in "
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<< "CodeEmitterGen::emitInstrOpBits()\n";
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abort();
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}
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}
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}
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unsigned numBits = BI->getNumBits();
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BitsInit *NewBI = new BitsInit(numBits);
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for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
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unsigned bitSwapIdx = numBits - bit - 1;
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Init *OrigBit = BI->getBit(bit);
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Init *BitSwap = BI->getBit(bitSwapIdx);
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NewBI->setBit(bit, BitSwap);
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NewBI->setBit(bitSwapIdx, OrigBit);
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}
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if (numBits % 2) {
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unsigned middle = (numBits + 1) / 2;
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NewBI->setBit(middle, BI->getBit(middle));
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}
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// Update the bits in reversed order so that emitInstrOpBits will get the
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// correct endianness.
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R->getValue("Inst")->setValue(NewBI);
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}
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}
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int CodeEmitterGen::getVariableBit(const std::string &VarName, BitsInit *BI, int bit){
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if (VarBitInit *VBI = dynamic_cast<VarBitInit*>(BI->getBit(bit))) {
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TypedInit *TI = VBI->getVariable();
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if (VarInit *VI = dynamic_cast<VarInit*>(TI)) {
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if (VI->getName() == VarName) return VBI->getBitNum();
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}
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}
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return -1;
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}
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void CodeEmitterGen::run(std::ostream &o) {
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CodeGenTarget Target;
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std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
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// For little-endian instruction bit encodings, reverse the bit order
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if (Target.isLittleEndianEncoding()) reverseBits(Insts);
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EmitSourceFileHeader("Machine Code Emitter", o);
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std::string Namespace = Insts[0]->getValueAsString("Namespace") + "::";
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@ -103,28 +97,6 @@ void CodeEmitterGen::run(std::ostream &o) {
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BitsInit *BI = R->getValueAsBitsInit("Inst");
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// For little-endian instruction bit encodings, reverse the bit order
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if (Target.isLittleEndianEncoding()) {
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unsigned numBits = BI->getNumBits();
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BitsInit *NewBI = new BitsInit(numBits);
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for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
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unsigned bitSwapIdx = numBits - bit - 1;
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Init *OrigBit = BI->getBit(bit);
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Init *BitSwap = BI->getBit(bitSwapIdx);
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NewBI->setBit(bit, BitSwap);
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NewBI->setBit(bitSwapIdx, OrigBit);
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}
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if (numBits % 2) {
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unsigned middle = (numBits + 1) / 2;
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NewBI->setBit(middle, BI->getBit(middle));
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}
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BI = NewBI;
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// Update the bits in reversed order so that emitInstrOpBits will get the
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// correct endianness.
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R->getValue("Inst")->setValue(NewBI);
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}
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unsigned Value = 0;
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const std::vector<RecordVal> &Vals = R->getValues();
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@ -137,136 +109,99 @@ void CodeEmitterGen::run(std::ostream &o) {
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o << " " << Value << "U";
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}
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o << "\n };\n";
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// Emit initial function code
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o << " const unsigned opcode = MI.getOpcode();\n"
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<< " unsigned Value = InstBits[opcode];\n"
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<< " switch (opcode) {\n";
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// Emit a case statement for each opcode
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for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
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I != E; ++I) {
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Record *R = *I;
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if (R->getName() == "PHI" || R->getName() == "INLINEASM") continue;
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// Map to accumulate all the cases.
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std::map<std::string, std::vector<std::string> > CaseMap;
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// Construct all cases statement for each opcode
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for (std::vector<Record*>::iterator IC = Insts.begin(), EC = Insts.end();
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IC != EC; ++IC) {
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Record *R = *IC;
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const std::string &InstName = R->getName();
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std::string Case("");
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if (InstName == "PHI" || InstName == "INLINEASM") continue;
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o << " case " << Namespace << R->getName() << ": {\n";
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BitsInit *BI = R->getValueAsBitsInit("Inst");
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const std::vector<RecordVal> &Vals = R->getValues();
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// Loop over all of the fields in the instruction, determining which are the
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// operands to the instruction.
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unsigned op = 0;
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std::map<std::string, unsigned> OpOrder;
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std::map<std::string, bool> OpContinuous;
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for (unsigned i = 0, e = Vals.size(); i != e; ++i) {
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if (!Vals[i].getPrefix() && !Vals[i].getValue()->isComplete()) {
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// Is the operand continuous? If so, we can just mask and OR it in
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// instead of doing it bit-by-bit, saving a lot in runtime cost.
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BitsInit *InstInit = BI;
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int beginBitInVar = -1, endBitInVar = -1;
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int beginBitInInst = -1, endBitInInst = -1;
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bool continuous = true;
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for (int bit = InstInit->getNumBits()-1; bit >= 0; --bit) {
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if (VarBitInit *VBI =
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dynamic_cast<VarBitInit*>(InstInit->getBit(bit))) {
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TypedInit *TI = VBI->getVariable();
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if (VarInit *VI = dynamic_cast<VarInit*>(TI)) {
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// only process the current variable
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if (VI->getName() != Vals[i].getName())
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continue;
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if (beginBitInVar == -1)
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beginBitInVar = VBI->getBitNum();
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if (endBitInVar == -1)
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endBitInVar = VBI->getBitNum();
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else {
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if (endBitInVar == (int)VBI->getBitNum() + 1)
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endBitInVar = VBI->getBitNum();
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else {
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continuous = false;
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break;
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}
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}
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if (beginBitInInst == -1)
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beginBitInInst = bit;
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if (endBitInInst == -1)
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endBitInInst = bit;
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else {
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if (endBitInInst == bit + 1)
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endBitInInst = bit;
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else {
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continuous = false;
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break;
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}
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}
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// maintain same distance between bits in field and bits in
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// instruction. if the relative distances stay the same
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// throughout,
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if (beginBitInVar - (int)VBI->getBitNum() !=
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beginBitInInst - bit) {
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continuous = false;
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break;
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}
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}
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}
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}
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// If we have found no bit in "Inst" which comes from this field, then
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// this is not an operand!!
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if (beginBitInInst != -1) {
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o << " // op" << op << ": " << Vals[i].getName() << "\n"
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<< " int op" << op
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<<" = getMachineOpValue(MI, MI.getOperand("<<op<<"));\n";
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//<< " MachineOperand &op" << op <<" = MI.getOperand("<<op<<");\n";
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OpOrder[Vals[i].getName()] = op++;
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DEBUG(o << " // Var: begin = " << beginBitInVar
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<< ", end = " << endBitInVar
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<< "; Inst: begin = " << beginBitInInst
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<< ", end = " << endBitInInst << "\n");
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if (continuous) {
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DEBUG(o << " // continuous: op" << OpOrder[Vals[i].getName()]
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<< "\n");
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// Mask off the right bits
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// Low mask (ie. shift, if necessary)
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assert(endBitInVar >= 0 && "Negative shift amount in masking!");
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if (endBitInVar != 0) {
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o << " op" << OpOrder[Vals[i].getName()]
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<< " >>= " << endBitInVar << ";\n";
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beginBitInVar -= endBitInVar;
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endBitInVar = 0;
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const std::string &VarName = Vals[i].getName();
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bool gotOp = false;
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for (int bit = BI->getNumBits()-1; bit >= 0; ) {
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int varBit = getVariableBit(VarName, BI, bit);
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if (varBit == -1) {
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--bit;
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} else {
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int beginInstBit = bit;
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int beginVarBit = varBit;
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int N = 1;
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for (--bit; bit >= 0;) {
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varBit = getVariableBit(VarName, BI, bit);
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if (varBit == -1 || varBit != (beginVarBit - N)) break;
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++N;
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--bit;
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}
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// High mask
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o << " op" << OpOrder[Vals[i].getName()]
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<< " &= (1<<" << beginBitInVar+1 << ") - 1;\n";
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// Shift the value to the correct place (according to place in inst)
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assert(endBitInInst >= 0 && "Negative shift amount!");
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if (endBitInInst != 0)
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o << " op" << OpOrder[Vals[i].getName()]
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<< " <<= " << endBitInInst << ";\n";
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// Just OR in the result
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o << " Value |= op" << OpOrder[Vals[i].getName()] << ";\n";
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if (!gotOp) {
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Case += " // op: " + VarName + "\n"
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+ " op = getMachineOpValue(MI, MI.getOperand("
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+ utostr(op++)
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+ "));\n";
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gotOp = true;
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}
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unsigned opMask = (1 << N) - 1;
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int opShift = beginVarBit - N + 1;
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opMask <<= opShift;
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opShift = beginInstBit - beginVarBit;
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if (opShift > 0) {
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Case += " Value |= (op & " + utostr(opMask) + "U) << "
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+ itostr(opShift) + ";\n";
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} else if (opShift < 0) {
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Case += " Value |= (op & " + utostr(opMask) + "U) >> "
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+ itostr(-opShift) + ";\n";
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} else {
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Case += " Value |= op & " + utostr(opMask) + "U;\n";
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}
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}
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// otherwise, will be taken care of in the loop below using this
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// value:
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OpContinuous[Vals[i].getName()] = continuous;
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}
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}
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}
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emitInstrOpBits(o, Vals, OpOrder, OpContinuous);
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std::vector<std::string> &InstList = CaseMap[Case];
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InstList.push_back(InstName);
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}
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// Emit initial function code
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o << " const unsigned opcode = MI.getOpcode();\n"
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<< " unsigned Value = InstBits[opcode];\n"
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<< " unsigned op;\n"
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<< " switch (opcode) {\n";
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// Emit each case statement
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std::map<std::string, std::vector<std::string> >::iterator IE, EE;
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for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) {
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const std::string &Case = IE->first;
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std::vector<std::string> &InstList = IE->second;
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for (int i = 0, N = InstList.size(); i < N; i++) {
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if (i) o << "\n";
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o << " case " << Namespace << InstList[i] << ":";
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}
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o << " {\n";
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o << Case;
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o << " break;\n"
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<< " }\n";
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}
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@ -17,10 +17,12 @@
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#include "TableGenBackend.h"
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#include <map>
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#include <vector>
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#include <string>
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namespace llvm {
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class RecordVal;
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class BitsInit;
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class CodeEmitterGen : public TableGenBackend {
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RecordKeeper &Records;
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@ -32,10 +34,8 @@ public:
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private:
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void emitMachineOpEmitter(std::ostream &o, const std::string &Namespace);
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void emitGetValueBit(std::ostream &o, const std::string &Namespace);
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void emitInstrOpBits(std::ostream &o,
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const std::vector<RecordVal> &Vals,
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std::map<std::string, unsigned> &OpOrder,
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std::map<std::string, bool> &OpContinuous);
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void reverseBits(std::vector<Record*> &Insts);
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int getVariableBit(const std::string &VarName, BitsInit *BI, int bit);
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};
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} // End llvm namespace
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