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XCore Target: correct callee save register spilling when callsUnwindInit is true.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198616 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Robert Lytton
2014-01-06 14:21:12 +00:00
parent 3a905cbce6
commit f1c1a7ce44
3 changed files with 120 additions and 5 deletions
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lib/Target/XCore/XCoreFrameLowering.cpp
+9 -1
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@@ -335,6 +335,9 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB,
for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
it != CSI.end(); ++it) {
unsigned Reg = it->getReg();
assert(Reg != XCore::LR && !(Reg == XCore::R10 && hasFP(*MF)) &&
"LR & FP are always handled in emitPrologue");
// Add the callee-saved register as live-in. It's killed at the spill.
MBB.addLiveIn(Reg);
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
@@ -355,7 +358,6 @@ restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
const TargetRegisterInfo *TRI) const{
MachineFunction *MF = MBB.getParent();
const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
bool AtStart = MI == MBB.begin();
MachineBasicBlock::iterator BeforeI = MI;
if (!AtStart)
@@ -363,6 +365,9 @@ restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
it != CSI.end(); ++it) {
unsigned Reg = it->getReg();
assert(Reg != XCore::LR && !(Reg == XCore::R10 && hasFP(*MF)) &&
"LR & FP are always handled in emitEpilogue");
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
TII.loadRegFromStackSlot(MBB, MI, Reg, it->getFrameIdx(), RC, TRI);
assert(MI != MBB.begin() &&
@@ -442,6 +447,9 @@ processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
if (!LRUsed && !MF.getFunction()->isVarArg() &&
MF.getFrameInfo()->estimateStackSize(MF))
LRUsed = true;
// We will be spilling all callee saved registers in case of unwinding.
if (MF.getMMI().callsUnwindInit())
LRUsed = true;
// We will handling LR in the prologue/epilogue
// and space on the stack ourselves.