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simplify getRegisterNumbering(). Remove the unused isSPVFP argument and
merge the common cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114013 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
7e2c04fd05
commit
f1c3eb37ae
@ -54,95 +54,44 @@ static cl::opt<bool>
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EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
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cl::desc("Enable use of a base pointer for complex stack frames"));
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unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
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bool *isSPVFP) {
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if (isSPVFP)
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*isSPVFP = false;
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unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned Reg) {
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using namespace ARM;
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switch (RegEnum) {
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switch (Reg) {
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default:
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llvm_unreachable("Unknown ARM register!");
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case R0: case D0: case Q0: return 0;
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case R1: case D1: case Q1: return 1;
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case R2: case D2: case Q2: return 2;
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case R3: case D3: case Q3: return 3;
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case R4: case D4: case Q4: return 4;
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case R5: case D5: case Q5: return 5;
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case R6: case D6: case Q6: return 6;
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case R7: case D7: case Q7: return 7;
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case R8: case D8: case Q8: return 8;
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case R9: case D9: case Q9: return 9;
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case R10: case D10: case Q10: return 10;
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case R11: case D11: case Q11: return 11;
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case R12: case D12: case Q12: return 12;
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case SP: case D13: case Q13: return 13;
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case LR: case D14: case Q14: return 14;
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case PC: case D15: case Q15: return 15;
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case R0: case S0: case D0: case Q0: return 0;
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case R1: case S1: case D1: case Q1: return 1;
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case R2: case S2: case D2: case Q2: return 2;
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case R3: case S3: case D3: case Q3: return 3;
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case R4: case S4: case D4: case Q4: return 4;
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case R5: case S5: case D5: case Q5: return 5;
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case R6: case S6: case D6: case Q6: return 6;
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case R7: case S7: case D7: case Q7: return 7;
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case R8: case S8: case D8: case Q8: return 8;
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case R9: case S9: case D9: case Q9: return 9;
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case R10: case S10: case D10: case Q10: return 10;
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case R11: case S11: case D11: case Q11: return 11;
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case R12: case S12: case D12: case Q12: return 12;
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case SP: case S13: case D13: case Q13: return 13;
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case LR: case S14: case D14: case Q14: return 14;
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case PC: case S15: case D15: case Q15: return 15;
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case D16: return 16;
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case D17: return 17;
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case D18: return 18;
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case D19: return 19;
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case D20: return 20;
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case D21: return 21;
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case D22: return 22;
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case D23: return 23;
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case D24: return 24;
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case D25: return 25;
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case D26: return 26;
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case D27: return 27;
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case D28: return 28;
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case D29: return 29;
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case D30: return 30;
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case D31: return 31;
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case S0: case S1: case S2: case S3:
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case S4: case S5: case S6: case S7:
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case S8: case S9: case S10: case S11:
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case S12: case S13: case S14: case S15:
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case S16: case S17: case S18: case S19:
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case S20: case S21: case S22: case S23:
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case S24: case S25: case S26: case S27:
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case S28: case S29: case S30: case S31: {
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if (isSPVFP)
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*isSPVFP = true;
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switch (RegEnum) {
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default: return 0; // Avoid compile time warning.
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case S0: return 0;
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case S1: return 1;
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case S2: return 2;
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case S3: return 3;
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case S4: return 4;
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case S5: return 5;
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case S6: return 6;
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case S7: return 7;
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case S8: return 8;
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case S9: return 9;
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case S10: return 10;
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case S11: return 11;
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case S12: return 12;
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case S13: return 13;
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case S14: return 14;
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case S15: return 15;
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case S16: return 16;
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case S17: return 17;
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case S18: return 18;
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case S19: return 19;
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case S20: return 20;
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case S21: return 21;
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case S22: return 22;
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case S23: return 23;
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case S24: return 24;
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case S25: return 25;
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case S26: return 26;
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case S27: return 27;
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case S28: return 28;
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case S29: return 29;
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case S30: return 30;
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case S31: return 31;
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}
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}
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case S16: case D16: return 16;
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case S17: case D17: return 17;
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case S18: case D18: return 18;
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case S19: case D19: return 19;
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case S20: case D20: return 20;
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case S21: case D21: return 21;
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case S22: case D22: return 22;
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case S23: case D23: return 23;
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case S24: case D24: return 24;
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case S25: case D25: return 25;
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case S26: case D26: return 26;
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case S27: case D27: return 27;
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case S28: case D28: return 28;
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case S29: case D29: return 29;
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case S30: case D30: return 30;
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case S31: case D31: return 31;
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}
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}
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@ -66,10 +66,8 @@ protected:
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public:
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/// getRegisterNumbering - Given the enum value for some register, e.g.
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/// ARM::LR, return the number that it corresponds to (e.g. 14). It
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/// also returns true in isSPVFP if the register is a single precision
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/// VFP register.
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static unsigned getRegisterNumbering(unsigned RegEnum, bool *isSPVFP = 0);
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/// ARM::LR, return the number that it corresponds to (e.g. 14).
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static unsigned getRegisterNumbering(unsigned Reg);
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/// Code Generation virtual methods...
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const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
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