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Move TableGen's register bank classes to their own source file.

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I'll be moving some more code there to gather all of the
register-specific stuff in one place. Currently it is shared between
CodeGenTarget and RegisterInfoEmitter.

The plan is that CodeGenRegisters can compute the full register bank
structure while RegisterInfoEmitter only will handle the printing part.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132788 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-06-09 18:42:07 +00:00
parent 372ab67ee8
commit f1e2b23dfa
3 changed files with 102 additions and 73 deletions
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1
utils/TableGen/CMakeLists.txt
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@ -16,6 +16,7 @@ add_llvm_utility(tblgen
CodeEmitterGen.cpp
CodeGenDAGPatterns.cpp
CodeGenInstruction.cpp
CodeGenRegisters.cpp
CodeGenTarget.cpp
DAGISelEmitter.cpp
DAGISelMatcherEmitter.cpp

101
utils/TableGen/CodeGenRegisters.cpp Normal file
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@ -0,0 +1,101 @@
//===- CodeGenRegisters.cpp - Register and RegisterClass Info -------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines structures to encapsulate information gleaned from the
// target register and register class definitions.
//
//===----------------------------------------------------------------------===//
#include "CodeGenRegisters.h"
#include "CodeGenTarget.h"
#include "llvm/ADT/StringExtras.h"
using namespace llvm;
//===----------------------------------------------------------------------===//
// CodeGenRegister
//===----------------------------------------------------------------------===//
CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) {
CostPerUse = R->getValueAsInt("CostPerUse");
}
const std::string &CodeGenRegister::getName() const {
return TheDef->getName();
}
//===----------------------------------------------------------------------===//
// CodeGenRegisterClass
//===----------------------------------------------------------------------===//
CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) {
// Rename anonymous register classes.
if (R->getName().size() > 9 && R->getName()[9] == '.') {
static unsigned AnonCounter = 0;
R->setName("AnonRegClass_"+utostr(AnonCounter++));
}
std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
Record *Type = TypeList[i];
if (!Type->isSubClassOf("ValueType"))
throw "RegTypes list member '" + Type->getName() +
"' does not derive from the ValueType class!";
VTs.push_back(getValueType(Type));
}
assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
std::vector<Record*> RegList = R->getValueAsListOfDefs("MemberList");
for (unsigned i = 0, e = RegList.size(); i != e; ++i) {
Record *Reg = RegList[i];
if (!Reg->isSubClassOf("Register"))
throw "Register Class member '" + Reg->getName() +
"' does not derive from the Register class!";
Elements.push_back(Reg);
}
// SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags.
ListInit *SRC = R->getValueAsListInit("SubRegClasses");
for (ListInit::const_iterator i = SRC->begin(), e = SRC->end(); i != e; ++i) {
DagInit *DAG = dynamic_cast<DagInit*>(*i);
if (!DAG) throw "SubRegClasses must contain DAGs";
DefInit *DAGOp = dynamic_cast<DefInit*>(DAG->getOperator());
Record *RCRec;
if (!DAGOp || !(RCRec = DAGOp->getDef())->isSubClassOf("RegisterClass"))
throw "Operator '" + DAG->getOperator()->getAsString() +
"' in SubRegClasses is not a RegisterClass";
// Iterate over args, all SubRegIndex instances.
for (DagInit::const_arg_iterator ai = DAG->arg_begin(), ae = DAG->arg_end();
ai != ae; ++ai) {
DefInit *Idx = dynamic_cast<DefInit*>(*ai);
Record *IdxRec;
if (!Idx || !(IdxRec = Idx->getDef())->isSubClassOf("SubRegIndex"))
throw "Argument '" + (*ai)->getAsString() +
"' in SubRegClasses is not a SubRegIndex";
if (!SubRegClasses.insert(std::make_pair(IdxRec, RCRec)).second)
throw "SubRegIndex '" + IdxRec->getName() + "' mentioned twice";
}
}
// Allow targets to override the size in bits of the RegisterClass.
unsigned Size = R->getValueAsInt("Size");
Namespace = R->getValueAsString("Namespace");
SpillSize = Size ? Size : EVT(VTs[0]).getSizeInBits();
SpillAlignment = R->getValueAsInt("Alignment");
CopyCost = R->getValueAsInt("CopyCost");
Allocatable = R->getValueAsBit("isAllocatable");
MethodBodies = R->getValueAsCode("MethodBodies");
MethodProtos = R->getValueAsCode("MethodProtos");
}
const std::string &CodeGenRegisterClass::getName() const {
return TheDef->getName();
}

73
utils/TableGen/CodeGenTarget.cpp
View File

@ -169,14 +169,6 @@ void CodeGenTarget::ReadRegisters() const {
Registers[i].EnumValue = i + 1;
}
CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) {
CostPerUse = R->getValueAsInt("CostPerUse");
}
const std::string &CodeGenRegister::getName() const {
return TheDef->getName();
}
void CodeGenTarget::ReadSubRegIndices() const {
SubRegIndices = Records.getAllDerivedDefinitions("SubRegIndex");
std::sort(SubRegIndices.begin(), SubRegIndices.end(), LessRecord());
@ -233,71 +225,6 @@ getRegisterVTs(Record *R) const {
}
CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) {
// Rename anonymous register classes.
if (R->getName().size() > 9 && R->getName()[9] == '.') {
static unsigned AnonCounter = 0;
R->setName("AnonRegClass_"+utostr(AnonCounter++));
}
std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
Record *Type = TypeList[i];
if (!Type->isSubClassOf("ValueType"))
throw "RegTypes list member '" + Type->getName() +
"' does not derive from the ValueType class!";
VTs.push_back(getValueType(Type));
}
assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
std::vector<Record*> RegList = R->getValueAsListOfDefs("MemberList");
for (unsigned i = 0, e = RegList.size(); i != e; ++i) {
Record *Reg = RegList[i];
if (!Reg->isSubClassOf("Register"))
throw "Register Class member '" + Reg->getName() +
"' does not derive from the Register class!";
Elements.push_back(Reg);
}
// SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags.
ListInit *SRC = R->getValueAsListInit("SubRegClasses");
for (ListInit::const_iterator i = SRC->begin(), e = SRC->end(); i != e; ++i) {
DagInit *DAG = dynamic_cast<DagInit*>(*i);
if (!DAG) throw "SubRegClasses must contain DAGs";
DefInit *DAGOp = dynamic_cast<DefInit*>(DAG->getOperator());
Record *RCRec;
if (!DAGOp || !(RCRec = DAGOp->getDef())->isSubClassOf("RegisterClass"))
throw "Operator '" + DAG->getOperator()->getAsString() +
"' in SubRegClasses is not a RegisterClass";
// Iterate over args, all SubRegIndex instances.
for (DagInit::const_arg_iterator ai = DAG->arg_begin(), ae = DAG->arg_end();
ai != ae; ++ai) {
DefInit *Idx = dynamic_cast<DefInit*>(*ai);
Record *IdxRec;
if (!Idx || !(IdxRec = Idx->getDef())->isSubClassOf("SubRegIndex"))
throw "Argument '" + (*ai)->getAsString() +
"' in SubRegClasses is not a SubRegIndex";
if (!SubRegClasses.insert(std::make_pair(IdxRec, RCRec)).second)
throw "SubRegIndex '" + IdxRec->getName() + "' mentioned twice";
}
}
// Allow targets to override the size in bits of the RegisterClass.
unsigned Size = R->getValueAsInt("Size");
Namespace = R->getValueAsString("Namespace");
SpillSize = Size ? Size : EVT(VTs[0]).getSizeInBits();
SpillAlignment = R->getValueAsInt("Alignment");
CopyCost = R->getValueAsInt("CopyCost");
Allocatable = R->getValueAsBit("isAllocatable");
MethodBodies = R->getValueAsCode("MethodBodies");
MethodProtos = R->getValueAsCode("MethodProtos");
}
const std::string &CodeGenRegisterClass::getName() const {
return TheDef->getName();
}
void CodeGenTarget::ReadLegalValueTypes() const {
const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
for (unsigned i = 0, e = RCs.size(); i != e; ++i)