mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-07-24 06:25:18 +00:00
[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191498 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -89,6 +89,11 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
|
||||
(hasMips64() && (isABI_N32() || isABI_N64()))) &&
|
||||
"Invalid Arch & ABI pair.");
|
||||
|
||||
if (hasMSA() && !isFP64bit())
|
||||
report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
|
||||
"See -mattr=+fp64.",
|
||||
false);
|
||||
|
||||
// Is the target system Linux ?
|
||||
if (TT.find("linux") == std::string::npos)
|
||||
IsLinux = false;
|
||||
|
Reference in New Issue
Block a user