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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191498 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
2013-09-27 10:08:31 +00:00
parent d2a31a124f
commit f1ef27e6e3
57 changed files with 68 additions and 58 deletions
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2
test/CodeGen/Mips/msa/arithmetic_float.ll
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@@ -1,4 +1,4 @@
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
define void @add_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
; CHECK: add_v4f32: