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Resynchronize isLoadFromStackSlot with LoadRegFromStackSlot (and stores) in PPCInstrInfo
These functions should have the same list of load/store instructions. Now that all load/store forms have been normalized (to single instructions or pseudos) they can be resynchronized. Found by inspection, although hopefully this will improve optimization. I've also added some comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178180 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -94,12 +94,18 @@ bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
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unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
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unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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int &FrameIndex) const {
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// Note: This list must be kept consistent with LoadRegFromStackSlot.
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switch (MI->getOpcode()) {
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switch (MI->getOpcode()) {
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default: break;
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default: break;
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case PPC::LD:
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case PPC::LD:
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case PPC::LWZ:
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case PPC::LWZ:
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case PPC::LFS:
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case PPC::LFS:
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case PPC::LFD:
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case PPC::LFD:
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case PPC::RESTORE_CR:
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case PPC::LVX:
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case PPC::RESTORE_VRSAVE:
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// Check for the operands added by addFrameReference (the immediate is the
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// offset which defaults to 0).
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if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
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if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
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MI->getOperand(2).isFI()) {
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MI->getOperand(2).isFI()) {
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FrameIndex = MI->getOperand(2).getIndex();
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FrameIndex = MI->getOperand(2).getIndex();
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@ -112,12 +118,18 @@ unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
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unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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int &FrameIndex) const {
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// Note: This list must be kept consistent with StoreRegToStackSlot.
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switch (MI->getOpcode()) {
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switch (MI->getOpcode()) {
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default: break;
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default: break;
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case PPC::STD:
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case PPC::STD:
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case PPC::STW:
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case PPC::STW:
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case PPC::STFS:
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case PPC::STFS:
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case PPC::STFD:
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case PPC::STFD:
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case PPC::SPILL_CR:
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case PPC::STVX:
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case PPC::SPILL_VRSAVE:
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// Check for the operands added by addFrameReference (the immediate is the
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// offset which defaults to 0).
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if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
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if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
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MI->getOperand(2).isFI()) {
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MI->getOperand(2).isFI()) {
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FrameIndex = MI->getOperand(2).getIndex();
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FrameIndex = MI->getOperand(2).getIndex();
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@ -441,6 +453,9 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
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const TargetRegisterClass *RC,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs,
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SmallVectorImpl<MachineInstr*> &NewMIs,
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bool &NonRI, bool &SpillsVRS) const{
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bool &NonRI, bool &SpillsVRS) const{
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// Note: If additional store instructions are added here,
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// update isStoreToStackSlot.
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DebugLoc DL;
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DebugLoc DL;
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if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
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if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
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NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
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NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
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@ -564,6 +579,9 @@ PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
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const TargetRegisterClass *RC,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs,
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SmallVectorImpl<MachineInstr*> &NewMIs,
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bool &NonRI, bool &SpillsVRS) const{
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bool &NonRI, bool &SpillsVRS) const{
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// Note: If additional load instructions are added here,
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// update isLoadFromStackSlot.
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if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
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if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
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NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
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NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
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DestReg), FrameIdx));
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DestReg), FrameIdx));
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