Add missing const qualifiers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37341 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/CodeGen/MachineInstr.h

@@ -415,15 +415,16 @@ public:
   /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
   /// the specific register or -1 if it is not found. It further tightening
   /// the search criteria to a use that kills the register if isKill is true.
-  int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false);
+  int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false) const;
   
   /// findRegisterDefOperand() - Returns the MachineOperand that is a def of
   /// the specific register or NULL if it is not found.
   MachineOperand *findRegisterDefOperand(unsigned Reg);
 
-  /// findFirstPredOperand() - Find the first operand in the operand list that
-  // is used to represent the predicate.
-  MachineOperand *findFirstPredOperand();
+  /// findFirstPredOperandIdx() - Find the index of the first operand in the
+  /// operand list that is used to represent the predicate. It returns -1 if
+  /// none is found.
+  int findFirstPredOperandIdx() const;
   
   /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
   ///

include/llvm/Target/TargetInstrInfo.h

@@ -395,19 +395,21 @@ public:
 
   /// isPredicable - Returns true if the instruction is already predicated.
   ///
-  virtual bool isPredicated(MachineInstr *MI) const {
+  virtual bool isPredicated(const MachineInstr *MI) const {
     return false;
   }
 
   /// PredicateInstruction - Convert the instruction into a predicated
   /// instruction. It returns true if the operation was successful.
-  virtual bool PredicateInstruction(MachineInstr *MI,
-                                    std::vector<MachineOperand> &Pred) const;
+  virtual
+  bool PredicateInstruction(MachineInstr *MI,
+                            const std::vector<MachineOperand> &Pred) const;
 
   /// SubsumesPredicate - Returns true if the first specified predicated
   /// subsumes the second, e.g. GE subsumes GT.
-  virtual bool SubsumesPredicate(std::vector<MachineOperand> &Pred1,
-                                 std::vector<MachineOperand> &Pred2) const {
+  virtual
+  bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
+                         const std::vector<MachineOperand> &Pred2) const {
     return false;
   }
 

lib/CodeGen/MachineInstr.cpp

@@ -191,9 +191,9 @@ bool MachineInstr::isPredicable() const {
 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
 /// the specific register or -1 if it is not found. It further tightening
 /// the search criteria to a use that kills the register if isKill is true.
-int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) {
+int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
-    MachineOperand &MO = getOperand(i);
+    const MachineOperand &MO = getOperand(i);
     if (MO.isReg() && MO.isUse() && MO.getReg() == Reg)
       if (!isKill || MO.isKill())
         return i;
@@ -212,17 +212,18 @@ MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
   return NULL;
 }
 
-/// findFirstPredOperand() - Find the first operand in the operand list that
-// is used to represent the predicate.
-MachineOperand *MachineInstr::findFirstPredOperand() {
+/// findFirstPredOperandIdx() - Find the index of the first operand in the
+/// operand list that is used to represent the predicate. It returns -1 if
+/// none is found.
+int MachineInstr::findFirstPredOperandIdx() const {
   const TargetInstrDescriptor *TID = getInstrDescriptor();
   if (TID->Flags & M_PREDICABLE) {
     for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
       if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND))
-        return &getOperand(i);
+        return i;
   }
 
-  return NULL;
+  return -1;
 }
   
 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.

lib/Target/TargetInstrInfo.cpp

@@ -61,7 +61,7 @@ MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const {
 }
 
 bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
-                                      std::vector<MachineOperand> &Pred) const {
+                                const std::vector<MachineOperand> &Pred) const {
   bool MadeChange = false;
   const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
   if (TID->Flags & M_PREDICABLE) {