[mips] [IAS] Add support for the XOR $reg,imm pseudo-instruction.

Summary:
This adds a MipsInstAlias which expands to XORi $reg,$reg,imm. For example, "xor $6, 0x3A" should be expanded to "xori $6, $6, 58".
This should work for all MIPS ISAs.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8284

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232473 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Toma Tabacu 2015-03-17 13:17:44 +00:00
parent 03b47b8e5b
commit f28b151b52
16 changed files with 17 additions and 0 deletions

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@ -1580,6 +1580,8 @@ def : MipsInstAlias<"sltu $rt, $rs, $imm",
(SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
def : MipsInstAlias<"xor $rs, $rt, $imm",
(XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
def : MipsInstAlias<"xor $rs, $imm",
(XORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
def : MipsInstAlias<"or $rs, $rt, $imm",
(ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
def : MipsInstAlias<"or $rs, $imm",

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@ -116,3 +116,4 @@
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]

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@ -165,3 +165,4 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]

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@ -228,3 +228,4 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]

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@ -195,3 +195,4 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]

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@ -233,4 +233,5 @@
trunc.w.s $f28,$f30
wsbh $k1,$9
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]

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@ -233,4 +233,5 @@
trunc.w.s $f28,$f30
wsbh $k1,$9
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]

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@ -233,4 +233,5 @@
trunc.w.s $f28,$f30
wsbh $k1,$9
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]

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@ -175,3 +175,4 @@
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]

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@ -257,3 +257,4 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]

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@ -259,3 +259,4 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]

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@ -276,3 +276,4 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]

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@ -302,4 +302,5 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
wsbh $k1,$9

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@ -302,4 +302,5 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
wsbh $k1,$9

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@ -302,4 +302,5 @@
trunc.w.d $f22,$f15
trunc.w.s $f28,$f30
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
wsbh $k1,$9

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@ -198,3 +198,4 @@
tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]