mirror of
https://github.com/c64scene-ar/llvm-6502.git
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ARM sched model: Add more ALU and CMP thumb instructions
Reapply of 183260. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183423 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Arnold Schwaighofer
parent
7de80e04d9
commit
f2988a0084
@ -310,7 +310,7 @@ def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
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let isNotDuplicable = 1, isCodeGenOnly = 1 in
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def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
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[(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
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T1Special<{0,0,?,?}> {
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T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
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// A8.6.6
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bits<3> dst;
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let Inst{6-3} = 0b1111; // Rm = pc
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@ -323,7 +323,7 @@ def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
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// probably because the instruction can be moved around.
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def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm),
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IIC_iALUi, "add", "\t$dst, $sp, $imm", []>,
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T1Encoding<{1,0,1,0,1,?}> {
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T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> {
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// A6.2 & A8.6.8
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bits<3> dst;
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bits<8> imm;
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@ -335,7 +335,7 @@ def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm),
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// ADD sp, sp, #<imm7>
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def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
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IIC_iALUi, "add", "\t$Rdn, $imm", []>,
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T1Misc<{0,0,0,0,0,?,?}> {
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T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> {
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// A6.2.5 & A8.6.8
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bits<7> imm;
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let Inst{6-0} = imm;
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@ -346,7 +346,7 @@ def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
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// FIXME: The encoding and the ASM string don't match up.
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def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
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IIC_iALUi, "sub", "\t$Rdn, $imm", []>,
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T1Misc<{0,0,0,0,1,?,?}> {
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T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> {
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// A6.2.5 & A8.6.214
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bits<7> imm;
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let Inst{6-0} = imm;
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@ -367,7 +367,7 @@ def : tInstAlias<"sub${p} sp, sp, $imm",
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// ADD <Rm>, sp
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def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
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"add", "\t$Rdn, $sp, $Rn", []>,
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T1Special<{0,0,?,?}> {
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T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
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// A8.6.9 Encoding T1
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bits<4> Rdn;
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let Inst{7} = Rdn{3};
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@ -379,7 +379,7 @@ def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
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// ADD sp, <Rm>
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def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
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"add", "\t$Rdn, $Rm", []>,
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T1Special<{0,0,?,?}> {
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T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
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// A8.6.9 Encoding T2
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bits<4> Rm;
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let Inst{7} = 1;
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@ -833,14 +833,15 @@ let isCommutable = 1, Uses = [CPSR] in
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def tADC : // A8.6.2
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T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
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"adc", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
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[(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
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// Add immediate
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def tADDi3 : // A8.6.4 T1
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T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
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IIC_iALUi,
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"add", "\t$Rd, $Rm, $imm3",
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[(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
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[(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
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Sched<[WriteALU]> {
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bits<3> imm3;
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let Inst{8-6} = imm3;
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}
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@ -849,7 +850,8 @@ def tADDi8 : // A8.6.4 T2
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T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
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(ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
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"add", "\t$Rdn, $imm8",
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[(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
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[(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
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Sched<[WriteALU]>;
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// Add register
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let isCommutable = 1 in
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@ -857,12 +859,12 @@ def tADDrr : // A8.6.6 T1
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T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iALUr,
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"add", "\t$Rd, $Rn, $Rm",
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[(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
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[(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
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let neverHasSideEffects = 1 in
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def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
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"add", "\t$Rdn, $Rm", []>,
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T1Special<{0,0,?,?}> {
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T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
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// A8.6.6 T2
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bits<4> Rdn;
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bits<4> Rm;
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@ -877,14 +879,15 @@ def tAND : // A8.6.12
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T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iBITr,
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"and", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
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[(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
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// ASR immediate
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def tASRri : // A8.6.14
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T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
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IIC_iMOVsi,
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"asr", "\t$Rd, $Rm, $imm5",
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[(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
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[(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
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Sched<[WriteALU]> {
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bits<5> imm5;
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let Inst{10-6} = imm5;
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}
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@ -894,14 +897,15 @@ def tASRrr : // A8.6.15
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T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iMOVsr,
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"asr", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
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[(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
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// BIC register
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def tBIC : // A8.6.20
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T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iBITr,
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"bic", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
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[(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>,
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Sched<[WriteALU]>;
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// CMN register
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let isCompare = 1, Defs = [CPSR] in {
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@ -917,7 +921,7 @@ def tCMNz : // A8.6.33
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T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iCMPr,
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"cmn", "\t$Rn, $Rm",
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[(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
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[(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>;
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} // isCompare = 1, Defs = [CPSR]
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@ -926,7 +930,7 @@ let isCompare = 1, Defs = [CPSR] in {
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def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
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"cmp", "\t$Rn, $imm8",
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[(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
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T1General<{1,0,1,?,?}> {
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T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> {
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// A8.6.35
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bits<3> Rn;
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bits<8> imm8;
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@ -939,11 +943,11 @@ def tCMPr : // A8.6.36 T1
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T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iCMPr,
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"cmp", "\t$Rn, $Rm",
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[(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
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[(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>;
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def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
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"cmp", "\t$Rn, $Rm", []>,
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T1Special<{0,1,?,?}> {
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T1Special<{0,1,?,?}>, Sched<[WriteCMP]> {
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// A8.6.36 T2
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bits<4> Rm;
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bits<4> Rn;
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@ -960,14 +964,15 @@ def tEOR : // A8.6.45
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T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iBITr,
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"eor", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
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[(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
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// LSL immediate
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def tLSLri : // A8.6.88
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T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
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IIC_iMOVsi,
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"lsl", "\t$Rd, $Rm, $imm5",
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[(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
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[(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>,
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Sched<[WriteALU]> {
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bits<5> imm5;
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let Inst{10-6} = imm5;
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}
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@ -977,14 +982,15 @@ def tLSLrr : // A8.6.89
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T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iMOVsr,
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"lsl", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
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[(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
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// LSR immediate
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def tLSRri : // A8.6.90
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T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
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IIC_iMOVsi,
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"lsr", "\t$Rd, $Rm, $imm5",
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[(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
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[(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
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Sched<[WriteALU]> {
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bits<5> imm5;
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let Inst{10-6} = imm5;
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}
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@ -994,14 +1000,14 @@ def tLSRrr : // A8.6.91
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T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iMOVsr,
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"lsr", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
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[(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
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// Move register
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let isMoveImm = 1 in
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def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
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"mov", "\t$Rd, $imm8",
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[(set tGPR:$Rd, imm0_255:$imm8)]>,
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T1General<{1,0,0,?,?}> {
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T1General<{1,0,0,?,?}>, Sched<[WriteALU]> {
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// A8.6.96
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bits<3> Rd;
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bits<8> imm8;
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@ -1019,7 +1025,7 @@ let neverHasSideEffects = 1 in {
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def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
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2, IIC_iMOVr,
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"mov", "\t$Rd, $Rm", "", []>,
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T1Special<{1,0,?,?}> {
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T1Special<{1,0,?,?}>, Sched<[WriteALU]> {
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// A8.6.97
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bits<4> Rd;
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bits<4> Rm;
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@ -1029,7 +1035,7 @@ def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
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}
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let Defs = [CPSR] in
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def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
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"movs\t$Rd, $Rm", []>, Encoding16 {
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"movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> {
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// A8.6.97
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bits<3> Rd;
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bits<3> Rm;
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@ -1060,7 +1066,7 @@ def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
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def tMVN : // A8.6.107
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T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
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"mvn", "\t$Rd, $Rn",
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[(set tGPR:$Rd, (not tGPR:$Rn))]>;
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[(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>;
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// Bitwise or register
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let isCommutable = 1 in
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@ -1068,7 +1074,7 @@ def tORR : // A8.6.114
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T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iBITr,
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"orr", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
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[(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
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// Swaps
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def tREV : // A8.6.134
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@ -1076,35 +1082,36 @@ def tREV : // A8.6.134
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IIC_iUNAr,
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"rev", "\t$Rd, $Rm",
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[(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
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Requires<[IsThumb, IsThumb1Only, HasV6]>;
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Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
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def tREV16 : // A8.6.135
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T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
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IIC_iUNAr,
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"rev16", "\t$Rd, $Rm",
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[(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
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Requires<[IsThumb, IsThumb1Only, HasV6]>;
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Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
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def tREVSH : // A8.6.136
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T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
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IIC_iUNAr,
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"revsh", "\t$Rd, $Rm",
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[(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
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Requires<[IsThumb, IsThumb1Only, HasV6]>;
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Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
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// Rotate right register
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def tROR : // A8.6.139
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T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iMOVsr,
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"ror", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
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[(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>,
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Sched<[WriteALU]>;
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// Negate register
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def tRSB : // A8.6.141
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T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
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IIC_iALUi,
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"rsb", "\t$Rd, $Rn, #0",
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[(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
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[(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>;
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// Subtract with carry register
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let Uses = [CPSR] in
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@ -1112,14 +1119,16 @@ def tSBC : // A8.6.151
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T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
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IIC_iALUr,
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"sbc", "\t$Rdn, $Rm",
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[(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
|
||||
[(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>,
|
||||
Sched<[WriteALU]>;
|
||||
|
||||
// Subtract immediate
|
||||
def tSUBi3 : // A8.6.210 T1
|
||||
T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
|
||||
IIC_iALUi,
|
||||
"sub", "\t$Rd, $Rm, $imm3",
|
||||
[(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
|
||||
[(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>,
|
||||
Sched<[WriteALU]> {
|
||||
bits<3> imm3;
|
||||
let Inst{8-6} = imm3;
|
||||
}
|
||||
@ -1128,14 +1137,16 @@ def tSUBi8 : // A8.6.210 T2
|
||||
T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn),
|
||||
(ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
|
||||
"sub", "\t$Rdn, $imm8",
|
||||
[(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
|
||||
[(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>,
|
||||
Sched<[WriteALU]>;
|
||||
|
||||
// Subtract register
|
||||
def tSUBrr : // A8.6.212
|
||||
T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
|
||||
IIC_iALUr,
|
||||
"sub", "\t$Rd, $Rn, $Rm",
|
||||
[(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
|
||||
[(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>,
|
||||
Sched<[WriteALU]>;
|
||||
|
||||
// Sign-extend byte
|
||||
def tSXTB : // A8.6.222
|
||||
@ -1143,7 +1154,8 @@ def tSXTB : // A8.6.222
|
||||
IIC_iUNAr,
|
||||
"sxtb", "\t$Rd, $Rm",
|
||||
[(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
|
||||
Requires<[IsThumb, IsThumb1Only, HasV6]>;
|
||||
Requires<[IsThumb, IsThumb1Only, HasV6]>,
|
||||
Sched<[WriteALU]>;
|
||||
|
||||
// Sign-extend short
|
||||
def tSXTH : // A8.6.224
|
||||
@ -1151,14 +1163,16 @@ def tSXTH : // A8.6.224
|
||||
IIC_iUNAr,
|
||||
"sxth", "\t$Rd, $Rm",
|
||||
[(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
|
||||
Requires<[IsThumb, IsThumb1Only, HasV6]>;
|
||||
Requires<[IsThumb, IsThumb1Only, HasV6]>,
|
||||
Sched<[WriteALU]>;
|
||||
|
||||
// Test
|
||||
let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
|
||||
def tTST : // A8.6.230
|
||||
T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
|
||||
"tst", "\t$Rn, $Rm",
|
||||
[(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
|
||||
[(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>,
|
||||
Sched<[WriteALU]>;
|
||||
|
||||
// Zero-extend byte
|
||||
def tUXTB : // A8.6.262
|
||||
@ -1166,7 +1180,8 @@ def tUXTB : // A8.6.262
|
||||
IIC_iUNAr,
|
||||
"uxtb", "\t$Rd, $Rm",
|
||||
[(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
|
||||
Requires<[IsThumb, IsThumb1Only, HasV6]>;
|
||||
Requires<[IsThumb, IsThumb1Only, HasV6]>,
|
||||
Sched<[WriteALU]>;
|
||||
|
||||
// Zero-extend short
|
||||
def tUXTH : // A8.6.264
|
||||
@ -1174,7 +1189,7 @@ def tUXTH : // A8.6.264
|
||||
IIC_iUNAr,
|
||||
"uxth", "\t$Rd, $Rm",
|
||||
[(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
|
||||
Requires<[IsThumb, IsThumb1Only, HasV6]>;
|
||||
Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
|
||||
|
||||
// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
|
||||
// Expanded after instruction selection into a branch sequence.
|
||||
@ -1189,7 +1204,7 @@ let usesCustomInserter = 1 in // Expanded after instruction selection.
|
||||
|
||||
def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
|
||||
IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
|
||||
T1Encoding<{1,0,1,0,0,?}> {
|
||||
T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> {
|
||||
bits<3> Rd;
|
||||
bits<8> addr;
|
||||
let Inst{10-8} = Rd;
|
||||
@ -1199,12 +1214,12 @@ def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
|
||||
|
||||
let neverHasSideEffects = 1, isReMaterializable = 1 in
|
||||
def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
|
||||
2, IIC_iALUi, []>;
|
||||
2, IIC_iALUi, []>, Sched<[WriteALU]>;
|
||||
|
||||
let hasSideEffects = 1 in
|
||||
def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
|
||||
(ins i32imm:$label, nohash_imm:$id, pred:$p),
|
||||
2, IIC_iALUi, []>;
|
||||
2, IIC_iALUi, []>, Sched<[WriteALU]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// TLS Instructions
|
||||
|
||||
Loading…
Reference in New Issue
Block a user