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R600: Fix LowerSDIV24
Use ComputeNumSignBits instead of checking for i8 / i16 which only worked when AMDIL was lying about having legal i8 / i16. If an integer is known to fit in 24-bits, we can do division faster with float ops. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213843 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
8971050012
commit
f303d037f2
@ -250,7 +250,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
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const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
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for (MVT VT : ScalarIntVTs) {
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setOperationAction(ISD::SREM, VT, Expand);
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setOperationAction(ISD::SDIV, VT, Expand);
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setOperationAction(ISD::SDIV, VT, Custom);
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// GPU does not have divrem function for signed or unsigned.
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setOperationAction(ISD::SDIVREM, VT, Custom);
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@ -1272,85 +1272,83 @@ SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
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return SDValue();
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}
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// This is a shortcut for integer division because we have fast i32<->f32
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// conversions, and fast f32 reciprocal instructions. The fractional part of a
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// float is enough to accurately represent up to a 24-bit integer.
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SDValue AMDGPUTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG &DAG) const {
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SDLoc DL(Op);
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EVT OVT = Op.getValueType();
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EVT VT = Op.getValueType();
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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MVT INTTY;
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MVT FLTTY;
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if (!OVT.isVector()) {
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INTTY = MVT::i32;
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FLTTY = MVT::f32;
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} else if (OVT.getVectorNumElements() == 2) {
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INTTY = MVT::v2i32;
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FLTTY = MVT::v2f32;
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} else if (OVT.getVectorNumElements() == 4) {
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INTTY = MVT::v4i32;
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FLTTY = MVT::v4f32;
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MVT IntVT = MVT::i32;
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MVT FltVT = MVT::f32;
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if (VT.isVector()) {
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unsigned NElts = VT.getVectorNumElements();
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IntVT = MVT::getVectorVT(MVT::i32, NElts);
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FltVT = MVT::getVectorVT(MVT::f32, NElts);
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}
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unsigned bitsize = OVT.getScalarType().getSizeInBits();
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unsigned BitSize = VT.getScalarType().getSizeInBits();
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// char|short jq = ia ^ ib;
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SDValue jq = DAG.getNode(ISD::XOR, DL, OVT, LHS, RHS);
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SDValue jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
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// jq = jq >> (bitsize - 2)
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jq = DAG.getNode(ISD::SRA, DL, OVT, jq, DAG.getConstant(bitsize - 2, OVT));
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jq = DAG.getNode(ISD::SRA, DL, VT, jq, DAG.getConstant(BitSize - 2, VT));
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// jq = jq | 0x1
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jq = DAG.getNode(ISD::OR, DL, OVT, jq, DAG.getConstant(1, OVT));
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jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, VT));
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// jq = (int)jq
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jq = DAG.getSExtOrTrunc(jq, DL, INTTY);
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jq = DAG.getSExtOrTrunc(jq, DL, IntVT);
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// int ia = (int)LHS;
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SDValue ia = DAG.getSExtOrTrunc(LHS, DL, INTTY);
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SDValue ia = DAG.getSExtOrTrunc(LHS, DL, IntVT);
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// int ib, (int)RHS;
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SDValue ib = DAG.getSExtOrTrunc(RHS, DL, INTTY);
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SDValue ib = DAG.getSExtOrTrunc(RHS, DL, IntVT);
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// float fa = (float)ia;
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SDValue fa = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ia);
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SDValue fa = DAG.getNode(ISD::SINT_TO_FP, DL, FltVT, ia);
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// float fb = (float)ib;
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SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ib);
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SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FltVT, ib);
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// float fq = native_divide(fa, fb);
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SDValue fq = DAG.getNode(ISD::FMUL, DL, FLTTY,
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fa, DAG.getNode(AMDGPUISD::RCP, DL, FLTTY, fb));
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SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
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fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
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// fq = trunc(fq);
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fq = DAG.getNode(ISD::FTRUNC, DL, FLTTY, fq);
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fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
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// float fqneg = -fq;
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SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FLTTY, fq);
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SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
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// float fr = mad(fqneg, fb, fa);
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SDValue fr = DAG.getNode(ISD::FADD, DL, FLTTY,
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DAG.getNode(ISD::MUL, DL, FLTTY, fqneg, fb), fa);
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SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT,
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DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa);
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// int iq = (int)fq;
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SDValue iq = DAG.getNode(ISD::FP_TO_SINT, DL, INTTY, fq);
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SDValue iq = DAG.getNode(ISD::FP_TO_SINT, DL, IntVT, fq);
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// fr = fabs(fr);
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fr = DAG.getNode(ISD::FABS, DL, FLTTY, fr);
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fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
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// fb = fabs(fb);
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fb = DAG.getNode(ISD::FABS, DL, FLTTY, fb);
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fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
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EVT SetCCVT = getSetCCResultType(*DAG.getContext(), VT);
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// int cv = fr >= fb;
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SDValue cv;
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if (INTTY == MVT::i32) {
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cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE);
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} else {
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cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE);
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}
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SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
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// jq = (cv ? jq : 0);
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jq = DAG.getNode(ISD::SELECT, DL, OVT, cv, jq,
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DAG.getConstant(0, OVT));
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jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, VT));
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// dst = iq + jq;
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iq = DAG.getSExtOrTrunc(iq, DL, OVT);
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iq = DAG.getNode(ISD::ADD, DL, OVT, iq, jq);
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return iq;
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iq = DAG.getSExtOrTrunc(iq, DL, VT);
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return DAG.getNode(ISD::ADD, DL, VT, iq, jq);
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}
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SDValue AMDGPUTargetLowering::LowerSDIV32(SDValue Op, SelectionDAG &DAG) const {
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@ -1425,19 +1423,20 @@ SDValue AMDGPUTargetLowering::LowerSDIV64(SDValue Op, SelectionDAG &DAG) const {
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SDValue AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const {
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EVT OVT = Op.getValueType().getScalarType();
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if (OVT == MVT::i64)
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return LowerSDIV64(Op, DAG);
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if (OVT == MVT::i32) {
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if (DAG.ComputeNumSignBits(Op.getOperand(0)) > 8 &&
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DAG.ComputeNumSignBits(Op.getOperand(1)) > 8) {
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// TODO: We technically could do this for i64, but shouldn't that just be
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// handled by something generally reducing 64-bit division on 32-bit
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// values to 32-bit?
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return LowerSDIV24(Op, DAG);
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}
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if (OVT.getScalarType() == MVT::i32)
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return LowerSDIV32(Op, DAG);
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if (OVT == MVT::i16 || OVT == MVT::i8) {
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// FIXME: We should be checking for the masked bits. This isn't reached
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// because i8 and i16 are not legal types.
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return LowerSDIV24(Op, DAG);
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}
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return SDValue(Op.getNode(), 0);
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assert(OVT == MVT::i64);
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return LowerSDIV64(Op, DAG);
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}
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SDValue AMDGPUTargetLowering::LowerSREM32(SDValue Op, SelectionDAG &DAG) const {
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120
test/CodeGen/R600/sdiv24.ll
Normal file
120
test/CodeGen/R600/sdiv24.ll
Normal file
@ -0,0 +1,120 @@
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; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; FUNC-LABEL: @sdiv24_i8
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; SI: V_CVT_F32_I32
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; SI: V_CVT_F32_I32
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; SI: V_RCP_F32
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; SI: V_CVT_I32_F32
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; EG: INT_TO_FLT
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; EG-DAG: INT_TO_FLT
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; EG-DAG: RECIP_IEEE
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; EG: FLT_TO_INT
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define void @sdiv24_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %in) {
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%den_ptr = getelementptr i8 addrspace(1)* %in, i8 1
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%num = load i8 addrspace(1) * %in
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%den = load i8 addrspace(1) * %den_ptr
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%result = sdiv i8 %num, %den
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store i8 %result, i8 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @sdiv24_i16
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; SI: V_CVT_F32_I32
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; SI: V_CVT_F32_I32
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; SI: V_RCP_F32
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; SI: V_CVT_I32_F32
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; EG: INT_TO_FLT
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; EG-DAG: INT_TO_FLT
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; EG-DAG: RECIP_IEEE
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; EG: FLT_TO_INT
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define void @sdiv24_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) {
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%den_ptr = getelementptr i16 addrspace(1)* %in, i16 1
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%num = load i16 addrspace(1) * %in, align 2
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%den = load i16 addrspace(1) * %den_ptr, align 2
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%result = sdiv i16 %num, %den
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store i16 %result, i16 addrspace(1)* %out, align 2
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ret void
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}
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; FUNC-LABEL: @sdiv24_i32
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; SI: V_CVT_F32_I32
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; SI: V_CVT_F32_I32
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; SI: V_RCP_F32
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; SI: V_CVT_I32_F32
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; EG: INT_TO_FLT
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; EG-DAG: INT_TO_FLT
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; EG-DAG: RECIP_IEEE
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; EG: FLT_TO_INT
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define void @sdiv24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in, align 4
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%den = load i32 addrspace(1) * %den_ptr, align 4
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%num.i24.0 = shl i32 %num, 8
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%den.i24.0 = shl i32 %den, 8
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%num.i24 = ashr i32 %num.i24.0, 8
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%den.i24 = ashr i32 %den.i24.0, 8
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%result = sdiv i32 %num.i24, %den.i24
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @sdiv25_i32
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; SI-NOT: V_CVT_F32_I32
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; SI-NOT: V_RCP_F32
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; EG-NOT: INT_TO_FLT
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; EG-NOT: RECIP_IEEE
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define void @sdiv25_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in, align 4
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%den = load i32 addrspace(1) * %den_ptr, align 4
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%num.i24.0 = shl i32 %num, 7
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%den.i24.0 = shl i32 %den, 7
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%num.i24 = ashr i32 %num.i24.0, 7
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%den.i24 = ashr i32 %den.i24.0, 7
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%result = sdiv i32 %num.i24, %den.i24
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @test_no_sdiv24_i32_1
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; SI-NOT: V_CVT_F32_I32
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; SI-NOT: V_RCP_F32
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; EG-NOT: INT_TO_FLT
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; EG-NOT: RECIP_IEEE
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define void @test_no_sdiv24_i32_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in, align 4
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%den = load i32 addrspace(1) * %den_ptr, align 4
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%num.i24.0 = shl i32 %num, 8
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%den.i24.0 = shl i32 %den, 7
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%num.i24 = ashr i32 %num.i24.0, 8
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%den.i24 = ashr i32 %den.i24.0, 7
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%result = sdiv i32 %num.i24, %den.i24
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @test_no_sdiv24_i32_2
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; SI-NOT: V_CVT_F32_I32
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; SI-NOT: V_RCP_F32
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; EG-NOT: INT_TO_FLT
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; EG-NOT: RECIP_IEEE
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define void @test_no_sdiv24_i32_2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in, align 4
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%den = load i32 addrspace(1) * %den_ptr, align 4
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%num.i24.0 = shl i32 %num, 7
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%den.i24.0 = shl i32 %den, 8
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%num.i24 = ashr i32 %num.i24.0, 7
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%den.i24 = ashr i32 %den.i24.0, 8
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%result = sdiv i32 %num.i24, %den.i24
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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