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Port SelectionDAG's ComputeNumSignBits-using code to instcombine,
now that instcombine also has ComputeNumSignBits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51350 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2085,7 +2085,7 @@ unsigned InstCombiner::ComputeNumSignBits(Value *V, unsigned Depth) const{
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case Instruction::AShr:
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Tmp = ComputeNumSignBits(U->getOperand(0), Depth+1);
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// SRA X, C -> adds C sign bits.
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// ashr X, C -> adds C sign bits.
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if (ConstantInt *C = dyn_cast<ConstantInt>(U->getOperand(1))) {
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Tmp += C->getZExtValue();
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if (Tmp > TyBits) Tmp = TyBits;
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@ -8195,6 +8195,33 @@ Instruction *InstCombiner::visitSExt(SExtInst &CI) {
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}
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}
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}
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// See if the value being truncated is already sign extended. If so, just
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// eliminate the trunc/sext pair.
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if (getOpcode(Src) == Instruction::Trunc) {
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Value *Op = cast<User>(Src)->getOperand(0);
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unsigned OpBits = cast<IntegerType>(Op->getType())->getBitWidth();
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unsigned MidBits = cast<IntegerType>(Src->getType())->getBitWidth();
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unsigned DestBits = cast<IntegerType>(CI.getType())->getBitWidth();
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unsigned NumSignBits = ComputeNumSignBits(Op);
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if (OpBits == DestBits) {
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// Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
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// bits, it is already ready.
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if (NumSignBits > DestBits-MidBits)
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return ReplaceInstUsesWith(CI, Op);
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} else if (OpBits < DestBits) {
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// Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
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// bits, just sext from i32.
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if (NumSignBits > OpBits-MidBits)
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return new SExtInst(Op, CI.getType(), "tmp");
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} else {
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// Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
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// bits, just truncate to i32.
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if (NumSignBits > OpBits-MidBits)
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return new TruncInst(Op, CI.getType(), "tmp");
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}
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}
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return 0;
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}
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@ -43,3 +43,10 @@ define i64 @voo(i32 %x) {
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%s = sext i32 %u to i64
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ret i64 %s
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}
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define i32 @woo(i8 %a, i32 %f, i1 %p, i32* %z) {
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%d = ashr i32 %f, 24
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%e = select i1 %p, i32 %d, i32 0
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%s = trunc i32 %e to i16
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%n = sext i16 %s to i32
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ret i32 %n
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}
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