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Teach SD some vector identities, allowing us to compile vec_set-9 into:

Browse Source 
_test3:
	movd	%rdi, %xmm1
	#IMPLICIT_DEF %xmm0
	punpcklqdq	%xmm1, %xmm0
	ret

instead of:

_test3:
	#IMPLICIT_DEF %rax
	movd	%rax, %xmm0
	movd	%rdi, %xmm1
	punpcklqdq	%xmm1, %xmm0
	ret

This is still not ideal.  There is no reason to two xmm regs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48058 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2008-03-08 23:43:36 +00:00
parent 19f7969f81
commit f3ba434781
2 changed files with 21 additions and 1 deletions
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14
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -1889,6 +1889,14 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
assert(MVT::isVector(VT) && !MVT::isVector(Operand.getValueType()) &&
MVT::getVectorElementType(VT) == Operand.getValueType() &&
"Illegal SCALAR_TO_VECTOR node!");
if (OpOpcode == ISD::UNDEF)
return getNode(ISD::UNDEF, VT);
// scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined.
if (OpOpcode == ISD::EXTRACT_VECTOR_ELT &&
isa<ConstantSDNode>(Operand.getOperand(1)) &&
Operand.getConstantOperandVal(1) == 0 &&
Operand.getOperand(0).getValueType() == VT)
return Operand.getOperand(0);
break;
case ISD::FNEG:
if (OpOpcode == ISD::FSUB) // -(X-Y) -> (Y-X)
@ -2039,6 +2047,10 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
case ISD::EXTRACT_VECTOR_ELT:
assert(N2C && "Bad EXTRACT_VECTOR_ELT!");
// EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF.
if (N1.getOpcode() == ISD::UNDEF)
return getNode(ISD::UNDEF, VT);
// EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is
// expanding copies of large vectors from registers.
if (N1.getOpcode() == ISD::CONCAT_VECTORS &&
@ -2054,7 +2066,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
// expanding large vector constants.
if (N1.getOpcode() == ISD::BUILD_VECTOR)
return N1.getOperand(N2C->getValue());
// EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector
// operations are lowered to scalars.
if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT)

8
test/CodeGen/X86/vec_set-9.ll Normal file
View File

@ -0,0 +1,8 @@
; RUN: llvm-as < %s | llc -march=x86-64 | grep movd | count 1
define <2 x i64> @test3(i64 %A) {
entry:
%B = insertelement <2 x i64> undef, i64 %A, i32 1
ret <2 x i64> %B
}