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[mips] Delete nodes and instructions for dynamic alloca that are no longer in
use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169580 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -205,9 +205,6 @@ def DSHD : SubwordSwap<0x24, 0x5, "dshd", CPU64Regs>;
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def LEA_ADDiu64 : EffectiveAddress<0x19,"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>;
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}
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let Uses = [SP_64], DecoderNamespace = "Mips64" in
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def DynAlloc64 : EffectiveAddress<0x19,"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>,
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Requires<[IsN64, HasStdEnc]>;
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let DecoderNamespace = "Mips64" in {
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def RDHWR64 : ReadHardware<CPU64Regs, HWRegs64>;
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@ -293,10 +290,6 @@ defm : SetgtPats<CPU64Regs, SLT64, SLTu64>;
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defm : SetgePats<CPU64Regs, SLT64, SLTu64>;
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defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>;
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// select MipsDynAlloc
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def : MipsPat<(MipsDynAlloc addr:$f), (DynAlloc64 addr:$f)>,
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Requires<[IsN64, HasStdEnc]>;
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// truncate
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def : MipsPat<(i32 (trunc CPU64Regs:$src)),
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(SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>,
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@ -169,7 +169,6 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
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case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
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case MipsISD::Wrapper: return "MipsISD::Wrapper";
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case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
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case MipsISD::Sync: return "MipsISD::Sync";
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case MipsISD::Ext: return "MipsISD::Ext";
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case MipsISD::Ins: return "MipsISD::Ins";
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@ -33,8 +33,6 @@ def SDT_MipsDivRem : SDTypeProfile<0, 2,
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def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
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def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>,
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SDTCisSameAs<0, 1>]>;
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def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
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def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
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@ -111,10 +109,6 @@ def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
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def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
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// Pointer to dynamically allocated stack area.
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def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc,
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[SDNPHasChain, SDNPInGlue]>;
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def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
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def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
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@ -1069,12 +1063,6 @@ let addr=0 in
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// can be matched. It's similar to Sparc LEA_ADDRi
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def LEA_ADDiu : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>;
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// DynAlloc node points to dynamically allocated stack space.
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// $sp is added to the list of implicitly used registers to prevent dead code
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// elimination from removing instructions that modify $sp.
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let Uses = [SP] in
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def DynAlloc : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>;
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// MADD*/MSUB*
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def MADD : MArithR<0, "madd", MipsMAdd, 1>;
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def MADDU : MArithR<1, "maddu", MipsMAddu, 1>;
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@ -1289,9 +1277,6 @@ defm : SetgtPats<CPURegs, SLT, SLTu>;
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defm : SetgePats<CPURegs, SLT, SLTu>;
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defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
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// select MipsDynAlloc
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def : MipsPat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
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// bswap pattern
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def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
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