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Expand unaligned loads/stores when the target doesn't support them. (PR1548)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40682 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Lauro Ramos Venancio
parent
4eda058550
commit
f3c13c82e3
@ -550,6 +550,93 @@ SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
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return Result;
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}
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/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
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static
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SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
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TargetLowering &TLI) {
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assert(MVT::isInteger(ST->getStoredVT()) &&
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"Non integer unaligned stores not implemented.");
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int SVOffset = ST->getSrcValueOffset();
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SDOperand Chain = ST->getChain();
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SDOperand Ptr = ST->getBasePtr();
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SDOperand Val = ST->getValue();
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MVT::ValueType VT = Val.getValueType();
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// Get the half-size VT
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MVT::ValueType NewStoredVT = ST->getStoredVT() - 1;
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int NumBits = MVT::getSizeInBits(NewStoredVT);
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int Alignment = ST->getAlignment();
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int IncrementSize = NumBits / 8;
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// Divide the stored value in two parts.
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SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
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SDOperand Lo = Val;
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SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
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// Store the two parts
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SDOperand Store1, Store2;
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Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
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ST->getSrcValue(), SVOffset, NewStoredVT,
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ST->isVolatile(), Alignment);
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Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
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DAG.getConstant(IncrementSize, TLI.getPointerTy()));
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Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
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ST->getSrcValue(), SVOffset + IncrementSize,
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NewStoredVT, ST->isVolatile(), Alignment);
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return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
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}
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/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
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static
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SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
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TargetLowering &TLI) {
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assert(MVT::isInteger(LD->getLoadedVT()) &&
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"Non integer unaligned loads not implemented.");
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int SVOffset = LD->getSrcValueOffset();
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SDOperand Chain = LD->getChain();
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SDOperand Ptr = LD->getBasePtr();
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MVT::ValueType VT = LD->getValueType(0);
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MVT::ValueType NewLoadedVT = LD->getLoadedVT() - 1;
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int NumBits = MVT::getSizeInBits(NewLoadedVT);
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int Alignment = LD->getAlignment();
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int IncrementSize = NumBits / 8;
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ISD::LoadExtType HiExtType = LD->getExtensionType();
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// If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
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if (HiExtType == ISD::NON_EXTLOAD)
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HiExtType = ISD::ZEXTLOAD;
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// Load the value in two parts
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SDOperand Lo, Hi;
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if (TLI.isLittleEndian()) {
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Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
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SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
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Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
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DAG.getConstant(IncrementSize, TLI.getPointerTy()));
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Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
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SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
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Alignment);
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} else {
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Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
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NewLoadedVT,LD->isVolatile(), Alignment);
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Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
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DAG.getConstant(IncrementSize, TLI.getPointerTy()));
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Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
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SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
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Alignment);
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}
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// aggregate the two parts
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SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
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SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
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Result = DAG.getNode(ISD::OR, VT, Result, Lo);
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SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
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Hi.getValue(1));
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SDOperand Ops[] = { Result, TF };
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return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
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}
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/// LegalizeOp - We know that the specified value has a legal type, and
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/// that its operands are legal. Now ensure that the operation itself
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@ -1507,7 +1594,22 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Legal: break;
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case TargetLowering::Legal:
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// If this is an unaligned load and the target doesn't support it,
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// expand it.
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if (!TLI.allowsUnalignedMemoryAccesses()) {
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unsigned ABIAlignment = TLI.getTargetData()->
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getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
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if (LD->getAlignment() < ABIAlignment){
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Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
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TLI);
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Tmp3 = Result.getOperand(0);
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Tmp4 = Result.getOperand(1);
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LegalizeOp(Tmp3);
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LegalizeOp(Tmp4);
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}
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}
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break;
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case TargetLowering::Custom:
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Tmp1 = TLI.LowerOperation(Tmp3, DAG);
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if (Tmp1.Val) {
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@ -1561,6 +1663,21 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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Tmp1 = LegalizeOp(Tmp3);
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Tmp2 = LegalizeOp(Tmp3.getValue(1));
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}
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} else {
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// If this is an unaligned load and the target doesn't support it,
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// expand it.
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if (!TLI.allowsUnalignedMemoryAccesses()) {
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unsigned ABIAlignment = TLI.getTargetData()->
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getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
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if (LD->getAlignment() < ABIAlignment){
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Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
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TLI);
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Tmp1 = Result.getOperand(0);
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Tmp2 = Result.getOperand(1);
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LegalizeOp(Tmp1);
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LegalizeOp(Tmp2);
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}
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}
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}
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break;
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case TargetLowering::Expand:
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@ -1810,7 +1927,17 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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MVT::ValueType VT = Tmp3.getValueType();
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switch (TLI.getOperationAction(ISD::STORE, VT)) {
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Legal: break;
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case TargetLowering::Legal:
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// If this is an unaligned store and the target doesn't support it,
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// expand it.
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if (!TLI.allowsUnalignedMemoryAccesses()) {
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unsigned ABIAlignment = TLI.getTargetData()->
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getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
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if (ST->getAlignment() < ABIAlignment)
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Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
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TLI);
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}
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break;
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case TargetLowering::Custom:
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Tmp1 = TLI.LowerOperation(Result, DAG);
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if (Tmp1.Val) Result = Tmp1;
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@ -1923,7 +2050,17 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
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switch (TLI.getStoreXAction(StVT)) {
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Legal: break;
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case TargetLowering::Legal:
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// If this is an unaligned store and the target doesn't support it,
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// expand it.
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if (!TLI.allowsUnalignedMemoryAccesses()) {
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unsigned ABIAlignment = TLI.getTargetData()->
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getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
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if (ST->getAlignment() < ABIAlignment)
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Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
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TLI);
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}
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break;
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case TargetLowering::Custom:
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Tmp1 = TLI.LowerOperation(Result, DAG);
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if (Tmp1.Val) Result = Tmp1;
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16
test/CodeGen/ARM/unaligned_load_store.ll
Normal file
16
test/CodeGen/ARM/unaligned_load_store.ll
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@ -0,0 +1,16 @@
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; RUN: llvm-as < %s | \
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; RUN: llc -march=arm -o %t -f
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; RUN: grep -c ldrb %t | grep 4
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; RUN: grep -c strb %t | grep 4
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%struct.p = type <{ i8, i32 }>
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@t = global %struct.p <{ i8 1, i32 10 }> ; <%struct.p*> [#uses=1]
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@u = weak global %struct.p zeroinitializer ; <%struct.p*> [#uses=1]
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define i32 @main() {
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entry:
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%tmp3 = load i32* getelementptr (%struct.p* @t, i32 0, i32 1), align 1 ; <i32> [#uses=2]
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store i32 %tmp3, i32* getelementptr (%struct.p* @u, i32 0, i32 1), align 1
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ret i32 %tmp3
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}
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