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Another minor refactoring for VLD1DUP instructions.

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The op11_8 field is the same for all of them so put it in the instruction
classes instead of specifying it separately for each instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120234 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-11-28 06:51:15 +00:00
parent 364a72a8e5
commit f3d2f9d4be
1 changed files with 20 additions and 22 deletions
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42
lib/Target/ARM/ARMInstrNEON.td
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@ -793,9 +793,8 @@ def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
// VLD1DUP : Vector Load (single element to all lanes) // VLD1DUP : Vector Load (single element to all lanes)
class VLD1DUP<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty, class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
PatFrag LoadOp> : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd), (ins addrmode6:$Rn),
: NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$Vd), (ins addrmode6:$Rn),
IIC_VLD1dup, "vld1", Dt, "\\{$Vd[]\\}, $Rn", "", IIC_VLD1dup, "vld1", Dt, "\\{$Vd[]\\}, $Rn", "",
[(set DPR:$Vd, (Ty (NEONvdup (i32 (LoadOp addrmode6:$Rn)))))]> { [(set DPR:$Vd, (Ty (NEONvdup (i32 (LoadOp addrmode6:$Rn)))))]> {
let Rm = 0b1111; let Rm = 0b1111;
@ -806,9 +805,9 @@ class VLD1QDUPPseudo<ValueType Ty, PatFrag LoadOp> : VLDQPseudo<IIC_VLD1dup> {
(Ty (NEONvdup (i32 (LoadOp addrmode6:$addr)))))]; (Ty (NEONvdup (i32 (LoadOp addrmode6:$addr)))))];
} }
def VLD1DUPd8 : VLD1DUP<0b1100, {0,0,0,?}, "8", v8i8, extloadi8>; def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
def VLD1DUPd16 : VLD1DUP<0b1100, {0,1,0,?}, "16", v4i16, extloadi16>; def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
def VLD1DUPd32 : VLD1DUP<0b1100, {1,0,0,?}, "32", v2i32, load>; def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
def VLD1DUPq8Pseudo : VLD1QDUPPseudo<v16i8, extloadi8>; def VLD1DUPq8Pseudo : VLD1QDUPPseudo<v16i8, extloadi8>;
def VLD1DUPq16Pseudo : VLD1QDUPPseudo<v8i16, extloadi16>; def VLD1DUPq16Pseudo : VLD1QDUPPseudo<v8i16, extloadi16>;
@ -816,40 +815,39 @@ def VLD1DUPq32Pseudo : VLD1QDUPPseudo<v4i32, load>;
let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
class VLD1QDUP<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty, class VLD1QDUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
PatFrag LoadOp> : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2),
: NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
(ins addrmode6:$Rn), IIC_VLD1dup, (ins addrmode6:$Rn), IIC_VLD1dup,
"vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> { "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
let Rm = 0b1111; let Rm = 0b1111;
let Inst{4} = Rn{4}; let Inst{4} = Rn{4};
} }
def VLD1DUPq8 : VLD1QDUP<0b1100, {0,0,1,0}, "8", v16i8, extloadi8>; def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8>;
def VLD1DUPq16 : VLD1QDUP<0b1100, {0,1,1,?}, "16", v8i16, extloadi16>; def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16>;
def VLD1DUPq32 : VLD1QDUP<0b1100, {1,0,1,?}, "32", v4i32, load>; def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load>;
// ...with address register writeback: // ...with address register writeback:
class VLD1DUPWB<bits<4> op11_8, bits<4> op7_4, string Dt> class VLD1DUPWB<bits<4> op7_4, string Dt>
: NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb), : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, GPR:$wb),
(ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1dupu, (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1dupu,
"vld1", Dt, "\\{$Vd[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> { "vld1", Dt, "\\{$Vd[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
let Inst{4} = Rn{4}; let Inst{4} = Rn{4};
} }
class VLD1QDUPWB<bits<4> op11_8, bits<4> op7_4, string Dt> class VLD1QDUPWB<bits<4> op7_4, string Dt>
: NLdSt<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb), : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
(ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1dupu, (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1dupu,
"vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> { "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
let Inst{4} = Rn{4}; let Inst{4} = Rn{4};
} }
def VLD1DUPd8_UPD : VLD1DUPWB<0b1100, {0,0,0,0}, "8">; def VLD1DUPd8_UPD : VLD1DUPWB<{0,0,0,0}, "8">;
def VLD1DUPd16_UPD : VLD1DUPWB<0b1100, {0,1,0,?}, "16">; def VLD1DUPd16_UPD : VLD1DUPWB<{0,1,0,?}, "16">;
def VLD1DUPd32_UPD : VLD1DUPWB<0b1100, {1,0,0,?}, "32">; def VLD1DUPd32_UPD : VLD1DUPWB<{1,0,0,?}, "32">;
def VLD1DUPq8_UPD : VLD1QDUPWB<0b1100, {0,0,1,0}, "8">; def VLD1DUPq8_UPD : VLD1QDUPWB<{0,0,1,0}, "8">;
def VLD1DUPq16_UPD : VLD1QDUPWB<0b1100, {0,1,1,?}, "16">; def VLD1DUPq16_UPD : VLD1QDUPWB<{0,1,1,?}, "16">;
def VLD1DUPq32_UPD : VLD1QDUPWB<0b1100, {1,0,1,?}, "32">; def VLD1DUPq32_UPD : VLD1QDUPWB<{1,0,1,?}, "32">;
def VLD1DUPq8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>; def VLD1DUPq8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
def VLD1DUPq16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>; def VLD1DUPq16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;