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R600: Add a pass that merge Vector Register

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Previously commited @183279 but tests were failing, reverted @183286
It was broken because @183336 was missing, now it's there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183343 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vincent Lejeune
2013-06-05 21:38:04 +00:00
parent f41d317054
commit f3d6e32c09
5 changed files with 400 additions and 0 deletions
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30
test/CodeGen/R600/texture-input-merge.ll Normal file
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@@ -0,0 +1,30 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
;CHECK-NOT: MOV
define void @test() {
%1 = call float @llvm.R600.load.input(i32 0)
%2 = call float @llvm.R600.load.input(i32 1)
%3 = call float @llvm.R600.load.input(i32 2)
%4 = call float @llvm.R600.load.input(i32 3)
%5 = fmul float %1, 3.0
%6 = fmul float %2, 3.0
%7 = fmul float %3, 3.0
%8 = fmul float %4, 3.0
%9 = insertelement <4 x float> undef, float %5, i32 0
%10 = insertelement <4 x float> %9, float %6, i32 1
%11 = insertelement <4 x float> undef, float %7, i32 0
%12 = insertelement <4 x float> %11, float %5, i32 1
%13 = insertelement <4 x float> undef, float %8, i32 0
%14 = call <4 x float> @llvm.R600.tex(<4 x float> %10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
%15 = call <4 x float> @llvm.R600.tex(<4 x float> %12, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
%16 = call <4 x float> @llvm.R600.tex(<4 x float> %13, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
%17 = fadd <4 x float> %14, %15
%18 = fadd <4 x float> %17, %16
call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 0)
ret void
}
declare float @llvm.R600.load.input(i32) readnone
declare <4 x float> @llvm.R600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone
declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)