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Misc. SSE2 intrinsics: clflush, lfench, mfence

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27699 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-04-14 07:43:12 +00:00
parent d9245ca1a1
commit f3e1b1d716
2 changed files with 17 additions and 2 deletions
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6
include/llvm/IntrinsicsX86.td
View File

@ -455,6 +455,12 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse2_maskmov_dqu : GCCBuiltin<"__builtin_ia32_maskmovdqu">,
Intrinsic<[llvm_void_ty, llvm_v16i8_ty,
llvm_v16i8_ty, llvm_ptr_ty], [IntrWriteMem]>;
def int_x86_sse2_clflush : GCCBuiltin<"__builtin_ia32_clflush">,
Intrinsic<[llvm_void_ty, llvm_ptr_ty], [IntrWriteMem]>;
def int_x86_sse2_lfence : GCCBuiltin<"__builtin_ia32_lfence">,
Intrinsic<[llvm_void_ty], [IntrWriteMem]>;
def int_x86_sse2_mfence : GCCBuiltin<"__builtin_ia32_mfence">,
Intrinsic<[llvm_void_ty], [IntrWriteMem]>;
}
//===----------------------------------------------------------------------===//

13
lib/Target/X86/X86InstrSSE.td
View File

@ -2002,12 +2002,21 @@ def MOVNTImr : I<0xC3, MRMDestMem, (ops i32mem:$dst, R32:$src),
[(int_x86_sse2_movnt_i addr:$dst, R32:$src)]>,
TB, Requires<[HasSSE2]>;
// Store fence
// Flush cache
def CLFLUSH : I<0xAE, MRM7m, (ops i8mem:$src),
"clflush $src", [(int_x86_sse2_clflush addr:$src)]>,
TB, Requires<[HasSSE2]>;
// Load, store, and memory fence
def SFENCE : I<0xAE, MRM7m, (ops),
"sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
def LFENCE : I<0xAE, MRM5m, (ops),
"lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
def MFENCE : I<0xAE, MRM6m, (ops),
"mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
// MXCSR register
def LDMXCSR : I<0xAE, MRM2m, (ops i32mem:$src),
def LDMXCSR : I<0xAE, MRM5m, (ops i32mem:$src),
"ldmxcsr $src",
[(int_x86_sse_ldmxcsr addr:$src)]>, TB, Requires<[HasSSE1]>;
def STMXCSR : I<0xAE, MRM3m, (ops i32mem:$dst),