mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-28 06:58:19 +00:00
simpilfy instruction encoding (and make the lines way shorter, aka Misha happification)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22499 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
parent
908bc862d5
commit
f3f951af3f
@ -1125,7 +1125,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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Opc = opcode == ISD::CTPOP ? Alpha::CTPOP :
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(opcode == ISD::CTTZ ? Alpha::CTTZ : Alpha::CTLZ);
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
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BuildMI(BB, Opc, 1, Result).addReg(Alpha::R31).addReg(Tmp1);
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return Result;
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case ISD::MULHU:
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@ -1331,7 +1331,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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Select(N.getOperand(0));
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// The chain for this call is now lowered.
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ExprMap.insert(std::make_pair(N.getValue(Node->getNumValues()-1), notIn));
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ExprMap[N.getValue(Node->getNumValues()-1)] = notIn;
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//grab the arguments
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std::vector<unsigned> argvregs;
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@ -1404,10 +1404,6 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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BuildMI(BB, Alpha::BSR, 1, Alpha::R26)
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.addGlobalAddress(GASD->getGlobal(),true);
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} else {
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//Must always reread relocation table before a call
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if (GASD)
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ExprMap.erase(N.getOperand(1));
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//no need to restore GP as we are doing an indirect call
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Tmp1 = SelectExpr(N.getOperand(1));
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BuildMI(BB, Alpha::BIS, 2, Alpha::R27).addReg(Tmp1).addReg(Tmp1);
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@ -1522,10 +1518,10 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
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break;
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}
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case MVT::i16:
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BuildMI(BB, Alpha::SEXTW, 1, Result).addReg(Tmp1);
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BuildMI(BB, Alpha::SEXTW, 1, Result).addReg(Alpha::R31).addReg(Tmp1);
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break;
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case MVT::i8:
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BuildMI(BB, Alpha::SEXTB, 1, Result).addReg(Tmp1);
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BuildMI(BB, Alpha::SEXTB, 1, Result).addReg(Alpha::R31).addReg(Tmp1);
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break;
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case MVT::i1:
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Tmp2 = MakeReg(MVT::i64);
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@ -2247,7 +2243,7 @@ void AlphaISel::Select(SDOperand N) {
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}
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// Just emit a 'ret' instruction
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AlphaLowering.restoreRA(BB);
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BuildMI(BB, Alpha::RET, 1, Alpha::R31).addReg(Alpha::R26);
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BuildMI(BB, Alpha::RET, 2, Alpha::R31).addReg(Alpha::R26).addImm(1);
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return;
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case ISD::TRUNCSTORE:
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@ -17,6 +17,12 @@
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//Floating-point
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//PALcode
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def u8imm : Operand<i8>;
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def s14imm : Operand<i16>;
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def s16imm : Operand<i16>;
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def s21imm : Operand<i32>;
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def s64imm : Operand<i64>;
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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@ -32,19 +38,53 @@ class InstAlpha<bits<6> op, dag OL, string asmstr> : Instruction { // A
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}
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//3.3.1
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class MForm<bits<6> opcode, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
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class MForm<bits<6> opcode, string asmstr>
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: InstAlpha<opcode, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), asmstr> {
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bits<5> Ra;
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bits<5> Rb;
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bits<16> disp;
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bits<5> Rb;
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let Inst{25-21} = Ra;
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let Inst{20-16} = Rb;
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let Inst{15-0} = disp;
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}
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class MgForm<bits<6> opcode, string asmstr>
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: InstAlpha<opcode, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB, s16imm:$NUM), asmstr> {
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bits<5> Ra;
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bits<16> disp;
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bits<5> Rb;
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let Inst{25-21} = Ra;
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let Inst{20-16} = Rb;
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let Inst{15-0} = disp;
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}
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class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
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bits<5> Ra;
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bits<5> Rb;
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bits<14> disp;
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let Inst{25-21} = Ra;
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let Inst{20-16} = Rb;
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let Inst{15-14} = TB;
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let Inst{13-0} = disp;
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}
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//3.3.2
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let isBranch = 1, isTerminator = 1 in
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class BForm<bits<6> opcode, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
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class BForm<bits<6> opcode, string asmstr>
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: InstAlpha<opcode, (ops GPRC:$RA, s21imm:$DISP), asmstr> {
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bits<5> Ra;
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bits<21> disp;
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let Inst{25-21} = Ra;
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let Inst{20-0} = disp;
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}
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let isBranch = 1, isTerminator = 1 in
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class FBForm<bits<6> opcode, string asmstr>
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: InstAlpha<opcode, (ops FPRC:$RA, s21imm:$DISP), asmstr> {
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bits<5> Ra;
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bits<21> disp;
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@ -53,23 +93,53 @@ class BForm<bits<6> opcode, dag OL, string asmstr> : InstAlpha<opcode, OL, asmst
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}
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//3.3.3
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class OForm<bits<6> opcode, bits<7> fun, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
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class OForm<bits<6> opcode, bits<7> fun, string asmstr>
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: InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), asmstr> {
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bits<5> Rc;
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bits<5> Ra;
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bits<5> Rb;
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bits<7> Function = fun;
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let Inst{25-21} = Ra;
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let Inst{20-16} = Rb;
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let Inst{15-13} = 0;
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let Inst{12} = 0;
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let Inst{11-5} = Function;
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let Inst{4-0} = Rc;
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}
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class OcmForm<bits<6> opcode, bits<7> fun, dag OL, string asmstr>
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: InstAlpha<opcode, OL, asmstr> {
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bits<5> Ra;
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bits<5> Rb;
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bits<3> SBZ;
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bits<7> Function = fun;
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bits<5> Rc;
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let Inst{25-21} = Ra;
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let Inst{20-16} = Rb;
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let Inst{15-13} = SBZ;
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let Inst{15-13} = 0;
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let Inst{12} = 0;
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let Inst{11-5} = Function;
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let Inst{4-0} = Rc;
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}
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class OFormL<bits<6> opcode, bits<7> fun, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> {
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class OFormL<bits<6> opcode, bits<7> fun, string asmstr>
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: InstAlpha<opcode, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), asmstr> {
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bits<5> Rc;
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bits<5> Ra;
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bits<8> LIT;
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bits<7> Function = fun;
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let Inst{25-21} = Ra;
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let Inst{20-13} = LIT;
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let Inst{12} = 1;
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let Inst{11-5} = Function;
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let Inst{4-0} = Rc;
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}
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class OcmFormL<bits<6> opcode, bits<7> fun, dag OL, string asmstr>
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: InstAlpha<opcode, OL, asmstr> {
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bits<5> Ra;
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bits<8> LIT;
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bits<7> Function = fun;
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@ -18,12 +18,6 @@ include "AlphaInstrFormats.td"
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// //#define GP $29
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// //#define SP $30
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def u8imm : Operand<i8>;
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def s14imm : Operand<i16>;
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def s16imm : Operand<i16>;
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def s21imm : Operand<i32>;
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def s64imm : Operand<i64>;
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def PHI : PseudoInstAlpha<(ops ), "#phi">;
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def IDEF : PseudoInstAlpha<(ops GPRC:$RA), "#idef $RA">;
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def WTF : PseudoInstAlpha<(ops ), "#wtf">;
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@ -41,10 +35,6 @@ def MEMLABEL : PseudoInstAlpha<(ops s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m),
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//T0-T7 = R1 - R8
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//T8-T11 = R22-R25
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let Defs = [R29] in
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let Uses = [R27] in
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def LDGP : PseudoInstAlpha<(ops), "ldgp $$29, 0($$27)">;
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//An even better improvement on the Int = SetCC(FP): SelectCC!
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//These are evil because they hide control flow in a MBB
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//really the ISel should emit multiple MBB
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@ -74,37 +64,37 @@ let isTwoAddress = 1 in {
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let isTwoAddress = 1 in {
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//conditional moves, int
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def CMOVEQ : OForm< 0x11, 0x24, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
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def CMOVEQ : OcmForm< 0x11, 0x24, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
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"cmoveq $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND = zero
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def CMOVEQi : OFormL< 0x11, 0x24, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
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def CMOVEQi : OcmFormL< 0x11, 0x24, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
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"cmoveq $RCOND,$L,$RDEST">; //CMOVE if RCOND = zero
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def CMOVGE : OForm< 0x11, 0x46, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
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def CMOVGE : OcmForm< 0x11, 0x46, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
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"cmovge $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND >= zero
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def CMOVGEi : OFormL< 0x11, 0x46, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
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def CMOVGEi : OcmFormL< 0x11, 0x46, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
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"cmovge $RCOND,$L,$RDEST">; //CMOVE if RCOND >= zero
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def CMOVGT : OForm< 0x11, 0x66, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
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def CMOVGT : OcmForm< 0x11, 0x66, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
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"cmovgt $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND > zero
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def CMOVGTi : OFormL< 0x11, 0x66, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
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def CMOVGTi : OcmFormL< 0x11, 0x66, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
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"cmovgt $RCOND,$L,$RDEST">; //CMOVE if RCOND > zero
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def CMOVLBC : OForm< 0x11, 0x16, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
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def CMOVLBC : OcmForm< 0x11, 0x16, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
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"cmovlbc $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND low bit clear
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def CMOVLBCi : OFormL< 0x11, 0x16, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
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def CMOVLBCi : OcmFormL< 0x11, 0x16, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
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"cmovlbc $RCOND,$L,$RDEST">; //CMOVE if RCOND low bit clear
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def CMOVLBS : OForm< 0x11, 0x14, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
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def CMOVLBS : OcmForm< 0x11, 0x14, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
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"cmovlbs $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND low bit set
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def CMOVLBSi : OFormL< 0x11, 0x14, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
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def CMOVLBSi : OcmFormL< 0x11, 0x14, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
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"cmovlbs $RCOND,$L,$RDEST">; //CMOVE if RCOND low bit set
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def CMOVLE : OForm< 0x11, 0x64, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
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def CMOVLE : OcmForm< 0x11, 0x64, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
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"cmovle $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND <= zero
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def CMOVLEi : OFormL< 0x11, 0x64, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
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def CMOVLEi : OcmFormL< 0x11, 0x64, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
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"cmovle $RCOND,$L,$RDEST">; //CMOVE if RCOND <= zero
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def CMOVLT : OForm< 0x11, 0x44, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
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def CMOVLT : OcmForm< 0x11, 0x44, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
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"cmovlt $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND < zero
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def CMOVLTi : OFormL< 0x11, 0x44, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
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def CMOVLTi : OcmFormL< 0x11, 0x44, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
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"cmovlt $RCOND,$L,$RDEST">; //CMOVE if RCOND < zero
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def CMOVNE : OForm< 0x11, 0x26, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
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def CMOVNE : OcmForm< 0x11, 0x26, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
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"cmovne $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND != zero
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def CMOVNEi : OFormL< 0x11, 0x26, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
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def CMOVNEi : OcmFormL< 0x11, 0x26, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
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"cmovne $RCOND,$L,$RDEST">; //CMOVE if RCOND != zero
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//conditional moves, fp
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@ -122,126 +112,124 @@ let isTwoAddress = 1 in {
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"fcmovne $RCOND,$RSRC,$RDEST">; //FCMOVE if != zero
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}
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def ADDL : OForm< 0x10, 0x00, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "addl $RA,$RB,$RC">; //Add longword
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def ADDLi : OFormL<0x10, 0x00, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "addl $RA,$L,$RC">; //Add longword
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def ADDQ : OForm< 0x10, 0x20, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "addq $RA,$RB,$RC">; //Add quadword
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def ADDQi : OFormL<0x10, 0x20, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "addq $RA,$L,$RC">; //Add quadword
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def AMASK : OForm< 0x11, 0x61, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "AMASK $RA,$RB,$RC">; //Architecture mask
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def AMASKi : OFormL<0x11, 0x61, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "AMASK $RA,$L,$RC">; //Architecture mask
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def AND : OForm< 0x11, 0x00, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "and $RA,$RB,$RC">; //Logical product
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def ANDi : OFormL<0x11, 0x00, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "and $RA,$L,$RC">; //Logical product
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def BIC : OForm< 0x11, 0x08, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "bic $RA,$RB,$RC">; //Bit clear
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def BICi : OFormL<0x11, 0x08, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "bic $RA,$L,$RC">; //Bit clear
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def BIS : OForm< 0x11, 0x20, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "bis $RA,$RB,$RC">; //Logical sum
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def BISi : OFormL<0x11, 0x20, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "bis $RA,$L,$RC">; //Logical sum
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def CTLZ : OForm< 0x1C, 0x32, (ops GPRC:$RC, GPRC:$RB), "CTLZ $RB,$RC">; //Count leading zero
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def CTPOP : OForm< 0x1C, 0x30, (ops GPRC:$RC, GPRC:$RB), "CTPOP $RB,$RC">; //Count population
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def CTTZ : OForm< 0x1C, 0x33, (ops GPRC:$RC, GPRC:$RB), "CTTZ $RB,$RC">; //Count trailing zero
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def EQV : OForm< 0x11, 0x48, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "eqv $RA,$RB,$RC">; //Logical equivalence
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def EQVi : OFormL<0x11, 0x48, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "eqv $RA,$L,$RC">; //Logical equivalence
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def EXTBL : OForm< 0x12, 0x06, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "EXTBL $RA,$RB,$RC">; //Extract byte low
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def EXTBLi : OFormL<0x12, 0x06, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "EXTBL $RA,$L,$RC">; //Extract byte low
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def EXTLH : OForm< 0x12, 0x6A, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "EXTLH $RA,$RB,$RC">; //Extract longword high
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def EXTLHi : OFormL<0x12, 0x6A, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "EXTLH $RA,$L,$RC">; //Extract longword high
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def EXTLL : OForm< 0x12, 0x26, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "EXTLL $RA,$RB,$RC">; //Extract longword low
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def EXTLLi : OFormL<0x12, 0x26, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "EXTLL $RA,$L,$RC">; //Extract longword low
|
||||
def EXTQH : OForm< 0x12, 0x7A, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "EXTQH $RA,$RB,$RC">; //Extract quadword high
|
||||
def EXTQHi : OFormL<0x12, 0x7A, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "EXTQH $RA,$L,$RC">; //Extract quadword high
|
||||
def EXTQ : OForm< 0x12, 0x36, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "EXTQ $RA,$RB,$RC">; //Extract quadword low
|
||||
def EXTQi : OFormL<0x12, 0x36, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "EXTQ $RA,$L,$RC">; //Extract quadword low
|
||||
def EXTWH : OForm< 0x12, 0x5A, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "EXTWH $RA,$RB,$RC">; //Extract word high
|
||||
def EXTWHi : OFormL<0x12, 0x5A, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "EXTWH $RA,$L,$RC">; //Extract word high
|
||||
def EXTWL : OForm< 0x12, 0x16, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "EXTWL $RA,$RB,$RC">; //Extract word low
|
||||
def EXTWLi : OFormL<0x12, 0x16, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "EXTWL $RA,$L,$RC">; //Extract word low
|
||||
def IMPLVER : OForm< 0x11, 0x6C, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "IMPLVER $RA,$RB,$RC">; //Implementation version
|
||||
def IMPLVERi : OFormL<0x11, 0x6C, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "IMPLVER $RA,$L,$RC">; //Implementation version
|
||||
def INSBL : OForm< 0x12, 0x0B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "INSBL $RA,$RB,$RC">; //Insert byte low
|
||||
def INSBLi : OFormL<0x12, 0x0B, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "INSBL $RA,$L,$RC">; //Insert byte low
|
||||
def INSLH : OForm< 0x12, 0x67, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "INSLH $RA,$RB,$RC">; //Insert longword high
|
||||
def INSLHi : OFormL<0x12, 0x67, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "INSLH $RA,$L,$RC">; //Insert longword high
|
||||
def INSLL : OForm< 0x12, 0x2B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "INSLL $RA,$RB,$RC">; //Insert longword low
|
||||
def INSLLi : OFormL<0x12, 0x2B, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "INSLL $RA,$L,$RC">; //Insert longword low
|
||||
def INSQH : OForm< 0x12, 0x77, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "INSQH $RA,$RB,$RC">; //Insert quadword high
|
||||
def INSQHi : OFormL<0x12, 0x77, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "INSQH $RA,$L,$RC">; //Insert quadword high
|
||||
def INSQL : OForm< 0x12, 0x3B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "INSQL $RA,$RB,$RC">; //Insert quadword low
|
||||
def INSQLi : OFormL<0x12, 0x3B, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "INSQL $RA,$L,$RC">; //Insert quadword low
|
||||
def INSWH : OForm< 0x12, 0x57, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "INSWH $RA,$RB,$RC">; //Insert word high
|
||||
def INSWHi : OFormL<0x12, 0x57, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "INSWH $RA,$L,$RC">; //Insert word high
|
||||
def INSWL : OForm< 0x12, 0x1B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "INSWL $RA,$RB,$RC">; //Insert word low
|
||||
def INSWLi : OFormL<0x12, 0x1B, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "INSWL $RA,$L,$RC">; //Insert word low
|
||||
def MSKBL : OForm< 0x12, 0x02, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MSKBL $RA,$RB,$RC">; //Mask byte low
|
||||
def MSKBLi : OFormL<0x12, 0x02, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "MSKBL $RA,$L,$RC">; //Mask byte low
|
||||
def MSKLH : OForm< 0x12, 0x62, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MSKLH $RA,$RB,$RC">; //Mask longword high
|
||||
def MSKLHi : OFormL<0x12, 0x62, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "MSKLH $RA,$L,$RC">; //Mask longword high
|
||||
def MSKLL : OForm< 0x12, 0x22, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MSKLL $RA,$RB,$RC">; //Mask longword low
|
||||
def MSKLLi : OFormL<0x12, 0x22, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "MSKLL $RA,$L,$RC">; //Mask longword low
|
||||
def MSKQH : OForm< 0x12, 0x72, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MSKQH $RA,$RB,$RC">; //Mask quadword high
|
||||
def MSKQHi : OFormL<0x12, 0x72, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "MSKQH $RA,$L,$RC">; //Mask quadword high
|
||||
def MSKQL : OForm< 0x12, 0x32, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MSKQL $RA,$RB,$RC">; //Mask quadword low
|
||||
def MSKQLi : OFormL<0x12, 0x32, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "MSKQL $RA,$L,$RC">; //Mask quadword low
|
||||
def MSKWH : OForm< 0x12, 0x52, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MSKWH $RA,$RB,$RC">; //Mask word high
|
||||
def MSKWHi : OFormL<0x12, 0x52, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "MSKWH $RA,$L,$RC">; //Mask word high
|
||||
def MSKWL : OForm< 0x12, 0x12, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MSKWL $RA,$RB,$RC">; //Mask word low
|
||||
def MSKWLi : OFormL<0x12, 0x12, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "MSKWL $RA,$L,$RC">; //Mask word low
|
||||
def MULL : OForm< 0x13, 0x00, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "mull $RA,$RB,$RC">; //Multiply longword
|
||||
def MULLi : OFormL<0x13, 0x00, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "mull $RA,$L,$RC">; //Multiply longword
|
||||
def MULQ : OForm< 0x13, 0x20, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "mulq $RA,$RB,$RC">; //Multiply quadword
|
||||
def MULQi : OFormL<0x13, 0x20, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "mulq $RA,$L,$RC">; //Multiply quadword
|
||||
def ORNOT : OForm< 0x11, 0x28, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "ornot $RA,$RB,$RC">; //Logical sum with complement
|
||||
def ORNOTi : OFormL<0x11, 0x28, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "ornot $RA,$L,$RC">; //Logical sum with complement
|
||||
def S4ADDL : OForm< 0x10, 0x02, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "s4addl $RA,$RB,$RC">; //Scaled add longword by 4
|
||||
def S4ADDLi : OFormL<0x10, 0x02, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "s4addl $RA,$L,$RC">; //Scaled add longword by 4
|
||||
def S4ADDQ : OForm< 0x10, 0x22, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "s4addq $RA,$RB,$RC">; //Scaled add quadword by 4
|
||||
def S4ADDQi : OFormL<0x10, 0x22, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "s4addq $RA,$L,$RC">; //Scaled add quadword by 4
|
||||
def S4SUBL : OForm< 0x10, 0x0B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "s4subl $RA,$RB,$RC">; //Scaled subtract longword by 4
|
||||
def S4SUBLi : OFormL<0x10, 0x0B, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "s4subl $RA,$L,$RC">; //Scaled subtract longword by 4
|
||||
def S4SUBQ : OForm< 0x10, 0x2B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "s4subq $RA,$RB,$RC">; //Scaled subtract quadword by 4
|
||||
def S4SUBQi : OFormL<0x10, 0x2B, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "s4subq $RA,$L,$RC">; //Scaled subtract quadword by 4
|
||||
def S8ADDL : OForm< 0x10, 0x12, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "s8addl $RA,$RB,$RC">; //Scaled add longword by 8
|
||||
def S8ADDLi : OFormL<0x10, 0x12, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "s8addl $RA,$L,$RC">; //Scaled add longword by 8
|
||||
def S8ADDQ : OForm< 0x10, 0x32, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "s8addq $RA,$RB,$RC">; //Scaled add quadword by 8
|
||||
def S8ADDQi : OFormL<0x10, 0x32, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "s8addq $RA,$L,$RC">; //Scaled add quadword by 8
|
||||
def S8SUBL : OForm< 0x10, 0x1B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "s8subl $RA,$RB,$RC">; //Scaled subtract longword by 8
|
||||
def S8SUBLi : OFormL<0x10, 0x1B, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "s8subl $RA,$L,$RC">; //Scaled subtract longword by 8
|
||||
def S8SUBQ : OForm< 0x10, 0x3B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "s8subq $RA,$RB,$RC">; //Scaled subtract quadword by 8
|
||||
def S8SUBQi : OFormL<0x10, 0x3B, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "s8subq $RA,$L,$RC">; //Scaled subtract quadword by 8
|
||||
def SEXTB : OForm< 0x1C, 0x00, (ops GPRC:$RC, GPRC:$RB), "sextb $RB,$RC">; //Sign extend byte
|
||||
def SEXTBi : OFormL<0x1C, 0x00, (ops GPRC:$RC, u8imm:$L), "sextb $L,$RC">; //Sign extend byte
|
||||
def SEXTW : OForm< 0x1C, 0x01, (ops GPRC:$RC, GPRC:$RB), "sextw $RB,$RC">; //Sign extend word
|
||||
def SEXTWi : OFormL<0x1C, 0x01, (ops GPRC:$RC, u8imm:$L), "sextw $L,$RC">; //Sign extend word
|
||||
def SL : OForm< 0x12, 0x39, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "sll $RA,$RB,$RC">; //Shift left logical
|
||||
def SLi : OFormL<0x12, 0x39, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "sll $RA,$L,$RC">; //Shift left logical
|
||||
def SRA : OForm< 0x12, 0x3C, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "sra $RA,$RB,$RC">; //Shift right arithmetic
|
||||
def SRAi : OFormL<0x12, 0x3C, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "sra $RA,$L,$RC">; //Shift right arithmetic
|
||||
def SRL : OForm< 0x12, 0x34, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "srl $RA,$RB,$RC">; //Shift right logical
|
||||
def ADDL : OForm< 0x10, 0x00, "addl $RA,$RB,$RC">; //Add longword
|
||||
def ADDLi : OFormL<0x10, 0x00, "addl $RA,$L,$RC">; //Add longword
|
||||
def ADDQ : OForm< 0x10, 0x20, "addq $RA,$RB,$RC">; //Add quadword
|
||||
def ADDQi : OFormL<0x10, 0x20, "addq $RA,$L,$RC">; //Add quadword
|
||||
def AMASK : OForm< 0x11, 0x61, "AMASK $RA,$RB,$RC">; //Architecture mask
|
||||
def AMASKi : OFormL<0x11, 0x61, "AMASK $RA,$L,$RC">; //Architecture mask
|
||||
def AND : OForm< 0x11, 0x00, "and $RA,$RB,$RC">; //Logical product
|
||||
def ANDi : OFormL<0x11, 0x00, "and $RA,$L,$RC">; //Logical product
|
||||
def BIC : OForm< 0x11, 0x08, "bic $RA,$RB,$RC">; //Bit clear
|
||||
def BICi : OFormL<0x11, 0x08, "bic $RA,$L,$RC">; //Bit clear
|
||||
def BIS : OForm< 0x11, 0x20, "bis $RA,$RB,$RC">; //Logical sum
|
||||
def BISi : OFormL<0x11, 0x20, "bis $RA,$L,$RC">; //Logical sum
|
||||
def CTLZ : OForm< 0x1C, 0x32, "CTLZ $RB,$RC">; //Count leading zero
|
||||
def CTPOP : OForm< 0x1C, 0x30, "CTPOP $RB,$RC">; //Count population
|
||||
def CTTZ : OForm< 0x1C, 0x33, "CTTZ $RB,$RC">; //Count trailing zero
|
||||
def EQV : OForm< 0x11, 0x48, "eqv $RA,$RB,$RC">; //Logical equivalence
|
||||
def EQVi : OFormL<0x11, 0x48, "eqv $RA,$L,$RC">; //Logical equivalence
|
||||
def EXTBL : OForm< 0x12, 0x06, "EXTBL $RA,$RB,$RC">; //Extract byte low
|
||||
def EXTBLi : OFormL<0x12, 0x06, "EXTBL $RA,$L,$RC">; //Extract byte low
|
||||
def EXTLH : OForm< 0x12, 0x6A, "EXTLH $RA,$RB,$RC">; //Extract longword high
|
||||
def EXTLHi : OFormL<0x12, 0x6A, "EXTLH $RA,$L,$RC">; //Extract longword high
|
||||
def EXTLL : OForm< 0x12, 0x26, "EXTLL $RA,$RB,$RC">; //Extract longword low
|
||||
def EXTLLi : OFormL<0x12, 0x26, "EXTLL $RA,$L,$RC">; //Extract longword low
|
||||
def EXTQH : OForm< 0x12, 0x7A, "EXTQH $RA,$RB,$RC">; //Extract quadword high
|
||||
def EXTQHi : OFormL<0x12, 0x7A, "EXTQH $RA,$L,$RC">; //Extract quadword high
|
||||
def EXTQ : OForm< 0x12, 0x36, "EXTQ $RA,$RB,$RC">; //Extract quadword low
|
||||
def EXTQi : OFormL<0x12, 0x36, "EXTQ $RA,$L,$RC">; //Extract quadword low
|
||||
def EXTWH : OForm< 0x12, 0x5A, "EXTWH $RA,$RB,$RC">; //Extract word high
|
||||
def EXTWHi : OFormL<0x12, 0x5A, "EXTWH $RA,$L,$RC">; //Extract word high
|
||||
def EXTWL : OForm< 0x12, 0x16, "EXTWL $RA,$RB,$RC">; //Extract word low
|
||||
def EXTWLi : OFormL<0x12, 0x16, "EXTWL $RA,$L,$RC">; //Extract word low
|
||||
def IMPLVER : OForm< 0x11, 0x6C, "IMPLVER $RA,$RB,$RC">; //Implementation version
|
||||
def IMPLVERi : OFormL<0x11, 0x6C, "IMPLVER $RA,$L,$RC">; //Implementation version
|
||||
def INSBL : OForm< 0x12, 0x0B, "INSBL $RA,$RB,$RC">; //Insert byte low
|
||||
def INSBLi : OFormL<0x12, 0x0B, "INSBL $RA,$L,$RC">; //Insert byte low
|
||||
def INSLH : OForm< 0x12, 0x67, "INSLH $RA,$RB,$RC">; //Insert longword high
|
||||
def INSLHi : OFormL<0x12, 0x67, "INSLH $RA,$L,$RC">; //Insert longword high
|
||||
def INSLL : OForm< 0x12, 0x2B, "INSLL $RA,$RB,$RC">; //Insert longword low
|
||||
def INSLLi : OFormL<0x12, 0x2B, "INSLL $RA,$L,$RC">; //Insert longword low
|
||||
def INSQH : OForm< 0x12, 0x77, "INSQH $RA,$RB,$RC">; //Insert quadword high
|
||||
def INSQHi : OFormL<0x12, 0x77, "INSQH $RA,$L,$RC">; //Insert quadword high
|
||||
def INSQL : OForm< 0x12, 0x3B, "INSQL $RA,$RB,$RC">; //Insert quadword low
|
||||
def INSQLi : OFormL<0x12, 0x3B, "INSQL $RA,$L,$RC">; //Insert quadword low
|
||||
def INSWH : OForm< 0x12, 0x57, "INSWH $RA,$RB,$RC">; //Insert word high
|
||||
def INSWHi : OFormL<0x12, 0x57, "INSWH $RA,$L,$RC">; //Insert word high
|
||||
def INSWL : OForm< 0x12, 0x1B, "INSWL $RA,$RB,$RC">; //Insert word low
|
||||
def INSWLi : OFormL<0x12, 0x1B, "INSWL $RA,$L,$RC">; //Insert word low
|
||||
def MSKBL : OForm< 0x12, 0x02, "MSKBL $RA,$RB,$RC">; //Mask byte low
|
||||
def MSKBLi : OFormL<0x12, 0x02, "MSKBL $RA,$L,$RC">; //Mask byte low
|
||||
def MSKLH : OForm< 0x12, 0x62, "MSKLH $RA,$RB,$RC">; //Mask longword high
|
||||
def MSKLHi : OFormL<0x12, 0x62, "MSKLH $RA,$L,$RC">; //Mask longword high
|
||||
def MSKLL : OForm< 0x12, 0x22, "MSKLL $RA,$RB,$RC">; //Mask longword low
|
||||
def MSKLLi : OFormL<0x12, 0x22, "MSKLL $RA,$L,$RC">; //Mask longword low
|
||||
def MSKQH : OForm< 0x12, 0x72, "MSKQH $RA,$RB,$RC">; //Mask quadword high
|
||||
def MSKQHi : OFormL<0x12, 0x72, "MSKQH $RA,$L,$RC">; //Mask quadword high
|
||||
def MSKQL : OForm< 0x12, 0x32, "MSKQL $RA,$RB,$RC">; //Mask quadword low
|
||||
def MSKQLi : OFormL<0x12, 0x32, "MSKQL $RA,$L,$RC">; //Mask quadword low
|
||||
def MSKWH : OForm< 0x12, 0x52, "MSKWH $RA,$RB,$RC">; //Mask word high
|
||||
def MSKWHi : OFormL<0x12, 0x52, "MSKWH $RA,$L,$RC">; //Mask word high
|
||||
def MSKWL : OForm< 0x12, 0x12, "MSKWL $RA,$RB,$RC">; //Mask word low
|
||||
def MSKWLi : OFormL<0x12, 0x12, "MSKWL $RA,$L,$RC">; //Mask word low
|
||||
def MULL : OForm< 0x13, 0x00, "mull $RA,$RB,$RC">; //Multiply longword
|
||||
def MULLi : OFormL<0x13, 0x00, "mull $RA,$L,$RC">; //Multiply longword
|
||||
def MULQ : OForm< 0x13, 0x20, "mulq $RA,$RB,$RC">; //Multiply quadword
|
||||
def MULQi : OFormL<0x13, 0x20, "mulq $RA,$L,$RC">; //Multiply quadword
|
||||
def ORNOT : OForm< 0x11, 0x28, "ornot $RA,$RB,$RC">; //Logical sum with complement
|
||||
def ORNOTi : OFormL<0x11, 0x28, "ornot $RA,$L,$RC">; //Logical sum with complement
|
||||
def S4ADDL : OForm< 0x10, 0x02, "s4addl $RA,$RB,$RC">; //Scaled add longword by 4
|
||||
def S4ADDLi : OFormL<0x10, 0x02, "s4addl $RA,$L,$RC">; //Scaled add longword by 4
|
||||
def S4ADDQ : OForm< 0x10, 0x22, "s4addq $RA,$RB,$RC">; //Scaled add quadword by 4
|
||||
def S4ADDQi : OFormL<0x10, 0x22, "s4addq $RA,$L,$RC">; //Scaled add quadword by 4
|
||||
def S4SUBL : OForm< 0x10, 0x0B, "s4subl $RA,$RB,$RC">; //Scaled subtract longword by 4
|
||||
def S4SUBLi : OFormL<0x10, 0x0B, "s4subl $RA,$L,$RC">; //Scaled subtract longword by 4
|
||||
def S4SUBQ : OForm< 0x10, 0x2B, "s4subq $RA,$RB,$RC">; //Scaled subtract quadword by 4
|
||||
def S4SUBQi : OFormL<0x10, 0x2B, "s4subq $RA,$L,$RC">; //Scaled subtract quadword by 4
|
||||
def S8ADDL : OForm< 0x10, 0x12, "s8addl $RA,$RB,$RC">; //Scaled add longword by 8
|
||||
def S8ADDLi : OFormL<0x10, 0x12, "s8addl $RA,$L,$RC">; //Scaled add longword by 8
|
||||
def S8ADDQ : OForm< 0x10, 0x32, "s8addq $RA,$RB,$RC">; //Scaled add quadword by 8
|
||||
def S8ADDQi : OFormL<0x10, 0x32, "s8addq $RA,$L,$RC">; //Scaled add quadword by 8
|
||||
def S8SUBL : OForm< 0x10, 0x1B, "s8subl $RA,$RB,$RC">; //Scaled subtract longword by 8
|
||||
def S8SUBLi : OFormL<0x10, 0x1B, "s8subl $RA,$L,$RC">; //Scaled subtract longword by 8
|
||||
def S8SUBQ : OForm< 0x10, 0x3B, "s8subq $RA,$RB,$RC">; //Scaled subtract quadword by 8
|
||||
def S8SUBQi : OFormL<0x10, 0x3B, "s8subq $RA,$L,$RC">; //Scaled subtract quadword by 8
|
||||
def SEXTB : OForm< 0x1C, 0x00, "sextb $RB,$RC">; //Sign extend byte
|
||||
def SEXTW : OForm< 0x1C, 0x01, "sextw $RB,$RC">; //Sign extend word
|
||||
def SL : OForm< 0x12, 0x39, "sll $RA,$RB,$RC">; //Shift left logical
|
||||
def SLi : OFormL<0x12, 0x39, "sll $RA,$L,$RC">; //Shift left logical
|
||||
def SRA : OForm< 0x12, 0x3C, "sra $RA,$RB,$RC">; //Shift right arithmetic
|
||||
def SRAi : OFormL<0x12, 0x3C, "sra $RA,$L,$RC">; //Shift right arithmetic
|
||||
def SRL : OForm< 0x12, 0x34, "srl $RA,$RB,$RC">; //Shift right logical
|
||||
|
||||
def SRLi : OFormL<0x12, 0x34, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "srl $RA,$L,$RC">; //Shift right logical
|
||||
def SUBL : OForm< 0x10, 0x09, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "subl $RA,$RB,$RC">; //Subtract longword
|
||||
def SUBLi : OFormL<0x10, 0x09, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "subl $RA,$L,$RC">; //Subtract longword
|
||||
def SUBQ : OForm< 0x10, 0x29, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "subq $RA,$RB,$RC">; //Subtract quadword
|
||||
def SUBQi : OFormL<0x10, 0x29, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "subq $RA,$L,$RC">; //Subtract quadword
|
||||
def UMULH : OForm< 0x13, 0x30, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "umulh $RA,$RB,$RC">; //Unsigned multiply quadword high
|
||||
def UMULHi : OFormL<0x13, 0x30, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "umulh $RA,$L,$RC">; //Unsigned multiply quadword high
|
||||
def XOR : OForm< 0x11, 0x40, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "xor $RA,$RB,$RC">; //Logical difference
|
||||
def XORi : OFormL<0x11, 0x40, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "xor $RA,$L,$RC">; //Logical difference
|
||||
def ZAP : OForm< 0x12, 0x30, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "zap $RA,$RB,$RC">; //Zero bytes
|
||||
def ZAPi : OFormL<0x12, 0x30, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "zap $RA,$L,$RC">; //Zero bytes
|
||||
def ZAPNOT : OForm< 0x12, 0x31, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "zapnot $RA,$RB,$RC">; //Zero bytes not
|
||||
def ZAPNOTi : OFormL<0x12, 0x31, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "zapnot $RA,$L,$RC">; //Zero bytes not
|
||||
def SRLi : OFormL<0x12, 0x34, "srl $RA,$L,$RC">; //Shift right logical
|
||||
def SUBL : OForm< 0x10, 0x09, "subl $RA,$RB,$RC">; //Subtract longword
|
||||
def SUBLi : OFormL<0x10, 0x09, "subl $RA,$L,$RC">; //Subtract longword
|
||||
def SUBQ : OForm< 0x10, 0x29, "subq $RA,$RB,$RC">; //Subtract quadword
|
||||
def SUBQi : OFormL<0x10, 0x29, "subq $RA,$L,$RC">; //Subtract quadword
|
||||
def UMULH : OForm< 0x13, 0x30, "umulh $RA,$RB,$RC">; //Unsigned multiply quadword high
|
||||
def UMULHi : OFormL<0x13, 0x30, "umulh $RA,$L,$RC">; //Unsigned multiply quadword high
|
||||
def XOR : OForm< 0x11, 0x40, "xor $RA,$RB,$RC">; //Logical difference
|
||||
def XORi : OFormL<0x11, 0x40, "xor $RA,$L,$RC">; //Logical difference
|
||||
def ZAP : OForm< 0x12, 0x30, "zap $RA,$RB,$RC">; //Zero bytes
|
||||
def ZAPi : OFormL<0x12, 0x30, "zap $RA,$L,$RC">; //Zero bytes
|
||||
def ZAPNOT : OForm< 0x12, 0x31, "zapnot $RA,$RB,$RC">; //Zero bytes not
|
||||
def ZAPNOTi : OFormL<0x12, 0x31, "zapnot $RA,$L,$RC">; //Zero bytes not
|
||||
|
||||
//Comparison, int
|
||||
def CMPBGE : OForm< 0x10, 0x0F, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "cmpbge $RA,$RB,$RC">; //Compare byte
|
||||
def CMPBGEi : OFormL<0x10, 0x0F, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "cmpbge $RA,$L,$RC">; //Compare byte
|
||||
def CMPEQ : OForm< 0x10, 0x2D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "cmpeq $RA,$RB,$RC">; //Compare signed quadword equal
|
||||
def CMPEQi : OFormL<0x10, 0x2D, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "cmpeq $RA,$L,$RC">; //Compare signed quadword equal
|
||||
def CMPLE : OForm< 0x10, 0x6D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "cmple $RA,$RB,$RC">; //Compare signed quadword less than or equal
|
||||
def CMPLEi : OFormL<0x10, 0x6D, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "cmple $RA,$L,$RC">; //Compare signed quadword less than or equal
|
||||
def CMPLT : OForm< 0x10, 0x4D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "cmplt $RA,$RB,$RC">; //Compare signed quadword less than
|
||||
def CMPLTi : OFormL<0x10, 0x4D, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "cmplt $RA,$L,$RC">; //Compare signed quadword less than
|
||||
def CMPULE : OForm< 0x10, 0x3D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "cmpule $RA,$RB,$RC">; //Compare unsigned quadword less than or equal
|
||||
def CMPULEi : OFormL<0x10, 0x3D, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "cmpule $RA,$L,$RC">; //Compare unsigned quadword less than or equal
|
||||
def CMPULT : OForm< 0x10, 0x1D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "cmpult $RA,$RB,$RC">; //Compare unsigned quadword less than
|
||||
def CMPULTi : OFormL<0x10, 0x1D, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "cmpult $RA,$L,$RC">; //Compare unsigned quadword less than
|
||||
def CMPBGE : OForm< 0x10, 0x0F, "cmpbge $RA,$RB,$RC">; //Compare byte
|
||||
def CMPBGEi : OFormL<0x10, 0x0F, "cmpbge $RA,$L,$RC">; //Compare byte
|
||||
def CMPEQ : OForm< 0x10, 0x2D, "cmpeq $RA,$RB,$RC">; //Compare signed quadword equal
|
||||
def CMPEQi : OFormL<0x10, 0x2D, "cmpeq $RA,$L,$RC">; //Compare signed quadword equal
|
||||
def CMPLE : OForm< 0x10, 0x6D, "cmple $RA,$RB,$RC">; //Compare signed quadword less than or equal
|
||||
def CMPLEi : OFormL<0x10, 0x6D, "cmple $RA,$L,$RC">; //Compare signed quadword less than or equal
|
||||
def CMPLT : OForm< 0x10, 0x4D, "cmplt $RA,$RB,$RC">; //Compare signed quadword less than
|
||||
def CMPLTi : OFormL<0x10, 0x4D, "cmplt $RA,$L,$RC">; //Compare signed quadword less than
|
||||
def CMPULE : OForm< 0x10, 0x3D, "cmpule $RA,$RB,$RC">; //Compare unsigned quadword less than or equal
|
||||
def CMPULEi : OFormL<0x10, 0x3D, "cmpule $RA,$L,$RC">; //Compare unsigned quadword less than or equal
|
||||
def CMPULT : OForm< 0x10, 0x1D, "cmpult $RA,$RB,$RC">; //Compare unsigned quadword less than
|
||||
def CMPULTi : OFormL<0x10, 0x1D, "cmpult $RA,$L,$RC">; //Compare unsigned quadword less than
|
||||
|
||||
//Comparison, FP
|
||||
def CMPTEQ : FPForm<0x16, 0x0A5, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cmpteq/su $RA,$RB,$RC">; //Compare T_floating equal
|
||||
@ -250,112 +238,116 @@ def CMPTLT : FPForm<0x16, 0x0A6, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cmptlt/su
|
||||
def CMPTUN : FPForm<0x16, 0x0A4, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cmptun/su $RA,$RB,$RC">; //Compare T_floating unordered
|
||||
|
||||
//There are in the Multimedia extentions, so let's not use them yet
|
||||
def MAXSB8 : OForm<0x1C, 0x3E, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MAXSB8 $RA,$RB,$RC">; //Vector signed byte maximum
|
||||
def MAXSW4 : OForm< 0x1C, 0x3F, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MAXSW4 $RA,$RB,$RC">; //Vector signed word maximum
|
||||
def MAXUB8 : OForm<0x1C, 0x3C, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MAXUB8 $RA,$RB,$RC">; //Vector unsigned byte maximum
|
||||
def MAXUW4 : OForm< 0x1C, 0x3D, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MAXUW4 $RA,$RB,$RC">; //Vector unsigned word maximum
|
||||
def MINSB8 : OForm< 0x1C, 0x38, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MINSB8 $RA,$RB,$RC">; //Vector signed byte minimum
|
||||
def MINSW4 : OForm< 0x1C, 0x39, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MINSW4 $RA,$RB,$RC">; //Vector signed word minimum
|
||||
def MINUB8 : OForm< 0x1C, 0x3A, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MINUB8 $RA,$RB,$RC">; //Vector unsigned byte minimum
|
||||
def MINUW4 : OForm< 0x1C, 0x3B, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "MINUW4 $RA,$RB,$RC">; //Vector unsigned word minimum
|
||||
def PERR : OForm< 0x1C, 0x31, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "PERR $RA,$RB,$RC">; //Pixel error
|
||||
def PKLB : OForm< 0x1C, 0x37, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "PKLB $RA,$RB,$RC">; //Pack longwords to bytes
|
||||
def PKWB : OForm<0x1C, 0x36, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "PKWB $RA,$RB,$RC">; //Pack words to bytes
|
||||
def UNPKBL : OForm< 0x1C, 0x35, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "UNPKBL $RA,$RB,$RC">; //Unpack bytes to longwords
|
||||
def UNPKBW : OForm< 0x1C, 0x34, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "UNPKBW $RA,$RB,$RC">; //Unpack bytes to words
|
||||
def MAXSB8 : OForm<0x1C, 0x3E, "MAXSB8 $RA,$RB,$RC">; //Vector signed byte maximum
|
||||
def MAXSW4 : OForm< 0x1C, 0x3F, "MAXSW4 $RA,$RB,$RC">; //Vector signed word maximum
|
||||
def MAXUB8 : OForm<0x1C, 0x3C, "MAXUB8 $RA,$RB,$RC">; //Vector unsigned byte maximum
|
||||
def MAXUW4 : OForm< 0x1C, 0x3D, "MAXUW4 $RA,$RB,$RC">; //Vector unsigned word maximum
|
||||
def MINSB8 : OForm< 0x1C, 0x38, "MINSB8 $RA,$RB,$RC">; //Vector signed byte minimum
|
||||
def MINSW4 : OForm< 0x1C, 0x39, "MINSW4 $RA,$RB,$RC">; //Vector signed word minimum
|
||||
def MINUB8 : OForm< 0x1C, 0x3A, "MINUB8 $RA,$RB,$RC">; //Vector unsigned byte minimum
|
||||
def MINUW4 : OForm< 0x1C, 0x3B, "MINUW4 $RA,$RB,$RC">; //Vector unsigned word minimum
|
||||
def PERR : OForm< 0x1C, 0x31, "PERR $RA,$RB,$RC">; //Pixel error
|
||||
def PKLB : OForm< 0x1C, 0x37, "PKLB $RA,$RB,$RC">; //Pack longwords to bytes
|
||||
def PKWB : OForm<0x1C, 0x36, "PKWB $RA,$RB,$RC">; //Pack words to bytes
|
||||
def UNPKBL : OForm< 0x1C, 0x35, "UNPKBL $RA,$RB,$RC">; //Unpack bytes to longwords
|
||||
def UNPKBW : OForm< 0x1C, 0x34, "UNPKBW $RA,$RB,$RC">; //Unpack bytes to words
|
||||
|
||||
//End operate
|
||||
|
||||
let isReturn = 1, isTerminator = 1 in
|
||||
def RET : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS), "ret $RD,($RS),1">; //Return from subroutine
|
||||
def RET : MbrForm< 0x1A, 0x02, (ops GPRC:$RD, GPRC:$RS, s64imm:$DISP), "ret $RD,($RS),$DISP">; //Return from subroutine
|
||||
|
||||
def JMP : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS), "jmp $RD,($RS),0">; //Jump
|
||||
def JMP : MbrForm< 0x1A, 0x00, (ops GPRC:$RD, GPRC:$RS, GPRC:$DISP), "jmp $RD,($RS),$DISP">; //Jump
|
||||
let isCall = 1,
|
||||
Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19,
|
||||
R20, R21, R22, R23, R24, R25, R27, R28, R29,
|
||||
F0, F1,
|
||||
F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
|
||||
F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30], Uses = [R29] in {
|
||||
def JSR : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr $RD,($RS),$DISP">; //Jump to subroutine
|
||||
def BSR : BForm<0x34, (ops GPRC:$RD, s21imm:$DISP), "bsr $RD,$DISP">; //Branch to subroutine
|
||||
def JSR : MbrForm< 0x1A, 0x01, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr $RD,($RS),$DISP">; //Jump to subroutine
|
||||
def BSR : BForm<0x34, "bsr $RA,$DISP">; //Branch to subroutine
|
||||
}
|
||||
let isCall = 1, Defs = [R24, R25, R27, R28], Uses = [R24, R25] in
|
||||
def JSRs : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr $RD,($RS),$DISP">; //Jump to div or rem
|
||||
def JSRs : MbrForm< 0x1A, 0x01, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr $RD,($RS),$DISP">; //Jump to div or rem
|
||||
|
||||
|
||||
def JSR_COROUTINE : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS), "jsr_coroutine $RD,($RS),1">; //Jump to subroutine return
|
||||
def BR : BForm<0x30, (ops GPRC:$RD, s21imm:$DISP), "br $RD,$DISP">; //Branch
|
||||
def JSR_COROUTINE : MbrForm< 0x1A, 0x03, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr_coroutine $RD,($RS),$DISP">; //Jump to subroutine return
|
||||
def BR : BForm<0x30, "br $RA,$DISP">; //Branch
|
||||
|
||||
//Stores, int
|
||||
def STB : MForm<0x0E, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stb $RA,$DISP($RB)">; // Store byte
|
||||
def STW : MForm<0x0D, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stw $RA,$DISP($RB)">; // Store word
|
||||
def STL : MForm<0x2C, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stl $RA,$DISP($RB)">; // Store longword
|
||||
def STQ : MForm<0x2D, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stq $RA,$DISP($RB)">; //Store quadword
|
||||
def STB : MForm<0x0E, "stb $RA,$DISP($RB)">; // Store byte
|
||||
def STW : MForm<0x0D, "stw $RA,$DISP($RB)">; // Store word
|
||||
def STL : MForm<0x2C, "stl $RA,$DISP($RB)">; // Store longword
|
||||
def STQ : MForm<0x2D, "stq $RA,$DISP($RB)">; //Store quadword
|
||||
|
||||
//Loads, int
|
||||
def LDL : MForm<0x28, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldl $RA,$DISP($RB)">; // Load sign-extended longword
|
||||
def LDQ : MForm<0x29, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB)">; //Load quadword
|
||||
def LDBU : MForm<0x0A, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldbu $RA,$DISP($RB)">; //Load zero-extended byte
|
||||
def LDWU : MForm<0x0C, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldwu $RA,$DISP($RB)">; //Load zero-extended word
|
||||
def LDL : MForm<0x28, "ldl $RA,$DISP($RB)">; // Load sign-extended longword
|
||||
def LDQ : MForm<0x29, "ldq $RA,$DISP($RB)">; //Load quadword
|
||||
def LDBU : MForm<0x0A, "ldbu $RA,$DISP($RB)">; //Load zero-extended byte
|
||||
def LDWU : MForm<0x0C, "ldwu $RA,$DISP($RB)">; //Load zero-extended word
|
||||
|
||||
//Stores, float
|
||||
def STS : MForm<0x26, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "sts $RA,$DISP($RB)">; //Store S_floating
|
||||
def STT : MForm<0x27, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "stt $RA,$DISP($RB)">; //Store T_floating
|
||||
def STS : MForm<0x26, "sts $RA,$DISP($RB)">; //Store S_floating
|
||||
def STT : MForm<0x27, "stt $RA,$DISP($RB)">; //Store T_floating
|
||||
|
||||
//Loads, float
|
||||
def LDS : MForm<0x22, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "lds $RA,$DISP($RB)">; //Load S_floating
|
||||
def LDT : MForm<0x23, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldt $RA,$DISP($RB)">; //Load T_floating
|
||||
def LDS : MForm<0x22, "lds $RA,$DISP($RB)">; //Load S_floating
|
||||
def LDT : MForm<0x23, "ldt $RA,$DISP($RB)">; //Load T_floating
|
||||
|
||||
//Load address
|
||||
def LDA : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "lda $RA,$DISP($RB)">; //Load address
|
||||
def LDAH : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldah $RA,$DISP($RB)">; //Load address high
|
||||
def LDA : MForm<0x08, "lda $RA,$DISP($RB)">; //Load address
|
||||
def LDAH : MForm<0x09, "ldah $RA,$DISP($RB)">; //Load address high
|
||||
|
||||
|
||||
//Loads, int, Rellocated Low form
|
||||
def LDLr : MForm<0x28, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldl $RA,$DISP($RB) !gprellow">; // Load sign-extended longword
|
||||
def LDQr : MForm<0x29, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB) !gprellow">; //Load quadword
|
||||
def LDBUr : MForm<0x0A, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldbu $RA,$DISP($RB) !gprellow">; //Load zero-extended byte
|
||||
def LDWUr : MForm<0x0C, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldwu $RA,$DISP($RB) !gprellow">; //Load zero-extended word
|
||||
def LDLr : MForm<0x28, "ldl $RA,$DISP($RB) !gprellow">; // Load sign-extended longword
|
||||
def LDQr : MForm<0x29, "ldq $RA,$DISP($RB) !gprellow">; //Load quadword
|
||||
def LDBUr : MForm<0x0A, "ldbu $RA,$DISP($RB) !gprellow">; //Load zero-extended byte
|
||||
def LDWUr : MForm<0x0C, "ldwu $RA,$DISP($RB) !gprellow">; //Load zero-extended word
|
||||
|
||||
//Loads, float, Rellocated Low form
|
||||
def LDSr : MForm<0x22, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "lds $RA,$DISP($RB) !gprellow">; //Load S_floating
|
||||
def LDTr : MForm<0x23, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldt $RA,$DISP($RB) !gprellow">; //Load T_floating
|
||||
def LDSr : MForm<0x22, "lds $RA,$DISP($RB) !gprellow">; //Load S_floating
|
||||
def LDTr : MForm<0x23, "ldt $RA,$DISP($RB) !gprellow">; //Load T_floating
|
||||
|
||||
//Load address, rellocated low and high form
|
||||
def LDAr : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "lda $RA,$DISP($RB) !gprellow">; //Load address
|
||||
def LDAHr : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldah $RA,$DISP($RB) !gprelhigh">; //Load address high
|
||||
def LDAr : MForm<0x08, "lda $RA,$DISP($RB) !gprellow">; //Load address
|
||||
def LDAHr : MForm<0x09, "ldah $RA,$DISP($RB) !gprelhigh">; //Load address high
|
||||
|
||||
//load address, rellocated gpdist form
|
||||
def LDAg : MgForm<0x08, "lda $RA,0($RB) !gpdisp!$NUM">; //Load address
|
||||
def LDAHg : MgForm<0x09, "ldah $RA,0($RB) !gpdisp!$NUM">; //Load address
|
||||
|
||||
|
||||
//Load quad, rellocated literal form
|
||||
def LDQl : MForm<0x29, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB) !literal">; //Load quadword
|
||||
def LDQl : MForm<0x29, "ldq $RA,$DISP($RB) !literal">; //Load quadword
|
||||
|
||||
//Stores, int
|
||||
def STBr : MForm<0x0E, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stb $RA,$DISP($RB) !gprellow">; // Store byte
|
||||
def STWr : MForm<0x0D, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stw $RA,$DISP($RB) !gprellow">; // Store word
|
||||
def STLr : MForm<0x2C, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stl $RA,$DISP($RB) !gprellow">; // Store longword
|
||||
def STQr : MForm<0x2D, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "stq $RA,$DISP($RB) !gprellow">; //Store quadword
|
||||
def STBr : MForm<0x0E, "stb $RA,$DISP($RB) !gprellow">; // Store byte
|
||||
def STWr : MForm<0x0D, "stw $RA,$DISP($RB) !gprellow">; // Store word
|
||||
def STLr : MForm<0x2C, "stl $RA,$DISP($RB) !gprellow">; // Store longword
|
||||
def STQr : MForm<0x2D, "stq $RA,$DISP($RB) !gprellow">; //Store quadword
|
||||
|
||||
//Stores, float
|
||||
def STSr : MForm<0x26, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "sts $RA,$DISP($RB) !gprellow">; //Store S_floating
|
||||
def STTr : MForm<0x27, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "stt $RA,$DISP($RB) !gprellow">; //Store T_floating
|
||||
def STSr : MForm<0x26, "sts $RA,$DISP($RB) !gprellow">; //Store S_floating
|
||||
def STTr : MForm<0x27, "stt $RA,$DISP($RB) !gprellow">; //Store T_floating
|
||||
|
||||
|
||||
//Branches, int
|
||||
def BEQ : BForm<0x39, (ops GPRC:$RA, s21imm:$DISP), "beq $RA,$DISP">; //Branch if = zero
|
||||
def BGE : BForm<0x3E, (ops GPRC:$RA, s21imm:$DISP), "bge $RA,$DISP">; //Branch if >= zero
|
||||
def BGT : BForm<0x3F, (ops GPRC:$RA, s21imm:$DISP), "bgt $RA,$DISP">; //Branch if > zero
|
||||
def BLBC : BForm<0x38, (ops GPRC:$RA, s21imm:$DISP), "blbc $RA,$DISP">; //Branch if low bit clear
|
||||
def BLBS : BForm<0x3C, (ops GPRC:$RA, s21imm:$DISP), "blbs $RA,$DISP">; //Branch if low bit set
|
||||
def BLE : BForm<0x3B, (ops GPRC:$RA, s21imm:$DISP), "ble $RA,$DISP">; //Branch if <= zero
|
||||
def BLT : BForm<0x3A, (ops GPRC:$RA, s21imm:$DISP), "blt $RA,$DISP">; //Branch if < zero
|
||||
def BNE : BForm<0x3D, (ops GPRC:$RA, s21imm:$DISP), "bne $RA,$DISP">; //Branch if != zero
|
||||
def BEQ : BForm<0x39, "beq $RA,$DISP">; //Branch if = zero
|
||||
def BGE : BForm<0x3E, "bge $RA,$DISP">; //Branch if >= zero
|
||||
def BGT : BForm<0x3F, "bgt $RA,$DISP">; //Branch if > zero
|
||||
def BLBC : BForm<0x38, "blbc $RA,$DISP">; //Branch if low bit clear
|
||||
def BLBS : BForm<0x3C, "blbs $RA,$DISP">; //Branch if low bit set
|
||||
def BLE : BForm<0x3B, "ble $RA,$DISP">; //Branch if <= zero
|
||||
def BLT : BForm<0x3A, "blt $RA,$DISP">; //Branch if < zero
|
||||
def BNE : BForm<0x3D, "bne $RA,$DISP">; //Branch if != zero
|
||||
|
||||
//Branches, float
|
||||
def FBEQ : BForm<0x31, (ops FPRC:$RA, s21imm:$DISP), "fbeq $RA,$DISP">; //Floating branch if = zero
|
||||
def FBGE : BForm<0x36, (ops FPRC:$RA, s21imm:$DISP), "fbge $RA,$DISP">; //Floating branch if >= zero
|
||||
def FBGT : BForm<0x37, (ops FPRC:$RA, s21imm:$DISP), "fbgt $RA,$DISP">; //Floating branch if > zero
|
||||
def FBLE : BForm<0x33, (ops FPRC:$RA, s21imm:$DISP), "fble $RA,$DISP">; //Floating branch if <= zero
|
||||
def FBLT : BForm<0x32, (ops FPRC:$RA, s21imm:$DISP), "fblt $RA,$DISP">; //Floating branch if < zero
|
||||
def FBNE : BForm<0x35, (ops FPRC:$RA, s21imm:$DISP), "fbne $RA,$DISP">; //Floating branch if != zero
|
||||
def FBEQ : FBForm<0x31, "fbeq $RA,$DISP">; //Floating branch if = zero
|
||||
def FBGE : FBForm<0x36, "fbge $RA,$DISP">; //Floating branch if >= zero
|
||||
def FBGT : FBForm<0x37, "fbgt $RA,$DISP">; //Floating branch if > zero
|
||||
def FBLE : FBForm<0x33, "fble $RA,$DISP">; //Floating branch if <= zero
|
||||
def FBLT : FBForm<0x32, "fblt $RA,$DISP">; //Floating branch if < zero
|
||||
def FBNE : FBForm<0x35, "fbne $RA,$DISP">; //Floating branch if != zero
|
||||
|
||||
//Funky Floating point ops
|
||||
def CPYS : FPForm<0x17, 0x020, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cpys $RA,$RB,$RC">; //Copy sign
|
||||
|
||||
Loading…
Reference in New Issue
Block a user