mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-07 16:54:48 +00:00
Update to in-place spilling framework. Includes live interval scaling and trivial rewriter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72729 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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@ -113,6 +113,26 @@ namespace llvm {
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VNInfoList valnos; // value#'s
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public:
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struct InstrSlots {
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enum {
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LOAD = 0,
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USE = 1,
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DEF = 2,
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STORE = 3,
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NUM = 4
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};
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static unsigned scale(unsigned slot, unsigned factor) {
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unsigned index = slot / NUM,
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offset = slot % NUM;
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assert(index <= ~0U / (factor * NUM) &&
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"Rescaled interval would overflow");
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return index * NUM * factor + offset;
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}
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};
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LiveInterval(unsigned Reg, float Weight, bool IsSS = false)
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: reg(Reg), weight(Weight), preference(0) {
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if (IsSS)
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@ -414,6 +434,10 @@ namespace llvm {
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/// Also remove the value# from value# list.
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void removeValNo(VNInfo *ValNo);
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/// scaleNumbering - Renumber VNI and ranges to provide gaps for new
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/// instructions.
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void scaleNumbering(unsigned factor);
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/// getSize - Returns the sum of sizes of all the LiveRange's.
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///
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unsigned getSize() const;
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@ -92,20 +92,12 @@ namespace llvm {
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std::vector<MachineInstr*> ClonedMIs;
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typedef LiveInterval::InstrSlots InstrSlots;
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public:
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static char ID; // Pass identification, replacement for typeid
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LiveIntervals() : MachineFunctionPass(&ID) {}
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struct InstrSlots {
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enum {
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LOAD = 0,
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USE = 1,
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DEF = 2,
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STORE = 3,
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NUM = 4
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};
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};
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static unsigned getBaseIndex(unsigned index) {
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return index - (index % InstrSlots::NUM);
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}
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@ -226,6 +218,13 @@ namespace llvm {
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return getInstructionFromIndex(Index) == 0;
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}
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/// hasGapAfterInstr - Return true if the successive instruction slot,
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/// i.e. Index + InstrSlots::Num, is not occupied.
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bool hasGapAfterInstr(unsigned Index) {
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Index = getBaseIndex(Index + InstrSlots::NUM);
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return getInstructionFromIndex(Index) == 0;
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}
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/// findGapBeforeInstr - Find an empty instruction slot before the
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/// specified index. If "Furthest" is true, find one that's furthest
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/// away from the index (but before any index that's occupied).
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@ -394,6 +393,10 @@ namespace llvm {
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/// computeNumbering - Compute the index numbering.
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void computeNumbering();
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/// scaleNumbering - Rescale interval numbers to introduce gaps for new
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/// instructions
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void scaleNumbering(int factor);
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/// intervalIsInOneMBB - Returns true if the specified interval is entirely
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/// within a single basic block.
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bool intervalIsInOneMBB(const LiveInterval &li) const;
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@ -48,6 +48,8 @@ namespace llvm {
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iterator begin() { return S2IMap.begin(); }
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iterator end() { return S2IMap.end(); }
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void scaleNumbering(int factor);
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unsigned getNumIntervals() const { return (unsigned)S2IMap.size(); }
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LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
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@ -359,6 +359,29 @@ void LiveInterval::removeValNo(VNInfo *ValNo) {
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}
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}
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/// scaleNumbering - Renumber VNI and ranges to provide gaps for new
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/// instructions.
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void LiveInterval::scaleNumbering(unsigned factor) {
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// Scale ranges.
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for (iterator RI = begin(), RE = end(); RI != RE; ++RI) {
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RI->start = InstrSlots::scale(RI->start, factor);
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RI->end = InstrSlots::scale(RI->end, factor);
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}
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// Scale VNI info.
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for (vni_iterator VNI = vni_begin(), VNIE = vni_end(); VNI != VNIE; ++VNI) {
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VNInfo *vni = *VNI;
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if (vni->def != ~0U && vni->def != ~1U) {
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vni->def = InstrSlots::scale(vni->def, factor);
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}
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for (unsigned i = 0; i < vni->kills.size(); ++i) {
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if (vni->kills[i] != 0)
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vni->kills[i] = InstrSlots::scale(vni->kills[i], factor);
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}
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}
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}
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/// getLiveRangeContaining - Return the live range that contains the
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/// specified index, or null if there is none.
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LiveInterval::const_iterator
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@ -36,6 +36,7 @@
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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#include <algorithm>
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#include <limits>
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#include <cmath>
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using namespace llvm;
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@ -243,6 +244,49 @@ void LiveIntervals::computeNumbering() {
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}
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}
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void LiveIntervals::scaleNumbering(int factor) {
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// Need to
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// * scale MBB begin and end points
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// * scale all ranges.
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// * Update VNI structures.
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// * Scale instruction numberings
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// Scale the MBB indices.
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Idx2MBBMap.clear();
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for (MachineFunction::iterator MBB = mf_->begin(), MBBE = mf_->end();
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MBB != MBBE; ++MBB) {
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std::pair<unsigned, unsigned> &mbbIndices = MBB2IdxMap[MBB->getNumber()];
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mbbIndices.first = InstrSlots::scale(mbbIndices.first, factor);
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mbbIndices.second = InstrSlots::scale(mbbIndices.second, factor);
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Idx2MBBMap.push_back(std::make_pair(mbbIndices.first, MBB));
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}
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std::sort(Idx2MBBMap.begin(), Idx2MBBMap.end(), Idx2MBBCompare());
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// Scale the intervals.
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for (iterator LI = begin(), LE = end(); LI != LE; ++LI) {
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LI->second->scaleNumbering(factor);
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}
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// Scale MachineInstrs.
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Mi2IndexMap oldmi2iMap = mi2iMap_;
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unsigned highestSlot = 0;
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for (Mi2IndexMap::iterator MI = oldmi2iMap.begin(), ME = oldmi2iMap.end();
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MI != ME; ++MI) {
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unsigned newSlot = InstrSlots::scale(MI->second, factor);
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mi2iMap_[MI->first] = newSlot;
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highestSlot = std::max(highestSlot, newSlot);
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}
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i2miMap_.clear();
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i2miMap_.resize(highestSlot + 1);
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for (Mi2IndexMap::iterator MI = mi2iMap_.begin(), ME = mi2iMap_.end();
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MI != ME; ++MI) {
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i2miMap_[MI->second] = MI->first;
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}
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}
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/// runOnMachineFunction - Register allocate the whole function
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///
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bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
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@ -15,15 +15,24 @@
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#define DEBUG_TYPE "livestacks"
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/Statistic.h"
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#include <limits>
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using namespace llvm;
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char LiveStacks::ID = 0;
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static RegisterPass<LiveStacks> X("livestacks", "Live Stack Slot Analysis");
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void LiveStacks::scaleNumbering(int factor) {
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// Scale the intervals.
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for (iterator LI = begin(), LE = end(); LI != LE; ++LI) {
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LI->second.scaleNumbering(factor);
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}
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}
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void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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@ -40,6 +40,8 @@
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#include <queue>
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#include <memory>
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#include <cmath>
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#include <iostream>
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using namespace llvm;
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STATISTIC(NumIters , "Number of iterations performed");
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@ -310,6 +312,93 @@ namespace {
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static RegisterPass<RALinScan>
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X("linearscan-regalloc", "Linear Scan Register Allocator");
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bool validateRegAlloc(MachineFunction *mf, LiveIntervals *lis,
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VirtRegMap *vrm) {
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MachineRegisterInfo *mri = &mf->getRegInfo();
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const TargetRegisterInfo *tri = mf->getTarget().getRegisterInfo();
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bool allocationValid = true;
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for (LiveIntervals::iterator itr = lis->begin(), end = lis->end();
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itr != end; ++itr) {
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LiveInterval *li = itr->second;
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if (TargetRegisterInfo::isPhysicalRegister(li->reg)) {
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continue;
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}
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if (vrm->hasPhys(li->reg)) {
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const TargetRegisterClass *trc = mri->getRegClass(li->reg);
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if (lis->hasInterval(vrm->getPhys(li->reg))) {
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if (li->overlaps(lis->getInterval(vrm->getPhys(li->reg)))) {
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std::cerr << "vreg " << li->reg << " overlaps its assigned preg "
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<< vrm->getPhys(li->reg) << "(" << tri->getName(vrm->getPhys(li->reg)) << ")\n";
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}
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}
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TargetRegisterClass::iterator fReg =
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std::find(trc->allocation_order_begin(*mf), trc->allocation_order_end(*mf),
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vrm->getPhys(li->reg));
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if (fReg == trc->allocation_order_end(*mf)) {
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std::cerr << "preg " << vrm->getPhys(li->reg)
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<< "(" << tri->getName(vrm->getPhys(li->reg)) << ") is not in the allocation set for vreg "
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<< li->reg << "\n";
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allocationValid &= false;
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}
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}
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else {
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std::cerr << "No preg for vreg " << li->reg << "\n";
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// What about conflicting loads/stores?
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continue;
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}
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for (LiveIntervals::iterator itr2 = next(itr); itr2 != end; ++itr2) {
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LiveInterval *li2 = itr2->second;
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if (li2->empty())
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continue;
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if (TargetRegisterInfo::isPhysicalRegister(li2->reg)) {
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if (li->overlaps(*li2)) {
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if (vrm->getPhys(li->reg) == li2->reg ||
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tri->areAliases(vrm->getPhys(li->reg), li2->reg)) {
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std::cerr << "vreg " << li->reg << " overlaps preg "
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<< li2->reg << "(" << tri->getName(li2->reg) << ") which aliases "
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<< vrm->getPhys(li->reg) << "(" << tri->getName(vrm->getPhys(li->reg)) << ")\n";
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allocationValid &= false;
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}
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}
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}
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else {
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if (!vrm->hasPhys(li2->reg)) {
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continue;
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}
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if (li->overlaps(*li2)) {
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if (vrm->getPhys(li->reg) == vrm->getPhys(li2->reg) ||
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tri->areAliases(vrm->getPhys(li->reg), vrm->getPhys(li2->reg))) {
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std::cerr << "vreg " << li->reg << " (preg " << vrm->getPhys(li->reg)
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<< ") overlaps vreg " << li2->reg << " (preg " << vrm->getPhys(li2->reg)
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<< ") and " << vrm->getPhys(li->reg) << " aliases " << vrm->getPhys(li2->reg) << "\n";
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allocationValid &= false;
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}
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}
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}
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}
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}
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return allocationValid;
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}
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void RALinScan::ComputeRelatedRegClasses() {
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// First pass, add all reg classes to the union, and determine at least one
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// reg class that each register is in.
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@ -430,16 +519,17 @@ bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
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if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
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if (NewSpillFramework) {
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spiller_.reset(createSpiller(mf_, li_, vrm_));
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spiller_.reset(createSpiller(mf_, li_, ls_, vrm_));
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}
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else {
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spiller_.reset(0);
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}
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initIntervalSets();
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linearScan();
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if (NewSpillFramework) {
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bool allocValid = validateRegAlloc(mf_, li_, vrm_);
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}
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// Rewrite spill code and update the PhysRegsUsed set.
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rewriter_->runOnMachineFunction(*mf_, *vrm_, li_);
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@ -454,6 +544,7 @@ bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
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NextReloadMap.clear();
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DowngradedRegs.clear();
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DowngradeMap.clear();
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spiller_.reset(0);
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return true;
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}
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@ -1127,8 +1218,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
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if (!NewSpillFramework) {
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added = li_->addIntervalsForSpills(*cur, spillIs, loopInfo, *vrm_);
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}
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else {
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} else {
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added = spiller_->spill(cur);
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}
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@ -1192,7 +1282,9 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
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// The earliest start of a Spilled interval indicates up to where
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// in handled we need to roll back
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unsigned earliestStart = cur->beginNumber();
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LiveInterval *earliestStartInterval = cur;
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// Spill live intervals of virtual regs mapped to the physical register we
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// want to clear (and its aliases). We only spill those that overlap with the
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@ -1201,17 +1293,48 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
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// mark our rollback point.
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std::vector<LiveInterval*> added;
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while (!spillIs.empty()) {
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bool epicFail = false;
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LiveInterval *sli = spillIs.back();
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spillIs.pop_back();
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DOUT << "\t\t\tspilling(a): " << *sli << '\n';
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earliestStart = std::min(earliestStart, sli->beginNumber());
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std::vector<LiveInterval*> newIs =
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li_->addIntervalsForSpills(*sli, spillIs, loopInfo, *vrm_);
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earliestStartInterval =
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(earliestStartInterval->beginNumber() < sli->beginNumber()) ?
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earliestStartInterval : sli;
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if (earliestStartInterval->beginNumber()!=earliestStart) {
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epicFail |= true;
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std::cerr << "What the 1 - "
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<< "earliestStart = " << earliestStart
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<< "earliestStartInterval = " << earliestStartInterval->beginNumber()
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<< "\n";
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}
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std::vector<LiveInterval*> newIs;
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if (!NewSpillFramework) {
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newIs = li_->addIntervalsForSpills(*sli, spillIs, loopInfo, *vrm_);
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} else {
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newIs = spiller_->spill(sli);
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}
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addStackInterval(sli, ls_, li_, mri_, *vrm_);
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std::copy(newIs.begin(), newIs.end(), std::back_inserter(added));
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spilled.insert(sli->reg);
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if (earliestStartInterval->beginNumber()!=earliestStart) {
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epicFail |= true;
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std::cerr << "What the 2 - "
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<< "earliestStart = " << earliestStart
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<< "earliestStartInterval = " << earliestStartInterval->beginNumber()
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<< "\n";
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}
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if (epicFail) {
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//abort();
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}
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}
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earliestStart = earliestStartInterval->beginNumber();
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DOUT << "\t\trolling back to: " << earliestStart << '\n';
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// Scan handled in reverse order up to the earliest start of a
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@ -2598,7 +2598,7 @@ void SimpleRegisterCoalescing::releaseMemory() {
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static bool isZeroLengthInterval(LiveInterval *li) {
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for (LiveInterval::Ranges::const_iterator
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i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
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if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
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if (i->end - i->start > LiveInterval::InstrSlots::NUM)
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return false;
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return true;
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}
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@ -133,7 +133,7 @@ namespace llvm {
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if (!li_->hasInterval(Reg))
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return 0;
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return li_->getApproximateInstructionCount(li_->getInterval(Reg)) *
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LiveIntervals::InstrSlots::NUM;
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LiveInterval::InstrSlots::NUM;
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}
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/// print - Implement the dump method.
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@ -12,6 +12,7 @@
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#include "Spiller.h"
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#include "VirtRegMap.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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@ -19,28 +20,105 @@
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/Debug.h"
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#include <algorithm>
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#include <map>
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using namespace llvm;
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Spiller::~Spiller() {}
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namespace {
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class TrivialSpiller : public Spiller {
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public:
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TrivialSpiller(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm) :
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mf(mf), lis(lis), vrm(vrm)
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/// Utility class for spillers.
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class SpillerBase : public Spiller {
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protected:
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MachineFunction *mf;
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LiveIntervals *lis;
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LiveStacks *ls;
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MachineFrameInfo *mfi;
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MachineRegisterInfo *mri;
|
||||
const TargetInstrInfo *tii;
|
||||
VirtRegMap *vrm;
|
||||
|
||||
/// Construct a spiller base.
|
||||
SpillerBase(MachineFunction *mf, LiveIntervals *lis, LiveStacks *ls, VirtRegMap *vrm) :
|
||||
mf(mf), lis(lis), ls(ls), vrm(vrm)
|
||||
{
|
||||
mfi = mf->getFrameInfo();
|
||||
mri = &mf->getRegInfo();
|
||||
tii = mf->getTarget().getInstrInfo();
|
||||
}
|
||||
|
||||
std::vector<LiveInterval*> spill(LiveInterval *li) {
|
||||
/// Insert a store of the given vreg to the given stack slot immediately
|
||||
/// after the given instruction. Returns the base index of the inserted
|
||||
/// instruction. The caller is responsible for adding an appropriate
|
||||
/// LiveInterval to the LiveIntervals analysis.
|
||||
unsigned insertStoreFor(MachineInstr *mi, unsigned ss,
|
||||
unsigned newVReg,
|
||||
const TargetRegisterClass *trc) {
|
||||
MachineBasicBlock::iterator nextInstItr(mi);
|
||||
++nextInstItr;
|
||||
|
||||
DOUT << "Trivial spiller spilling " << *li << "\n";
|
||||
if (!lis->hasGapAfterInstr(lis->getInstructionIndex(mi))) {
|
||||
lis->scaleNumbering(2);
|
||||
ls->scaleNumbering(2);
|
||||
}
|
||||
|
||||
unsigned miIdx = lis->getInstructionIndex(mi);
|
||||
|
||||
assert(lis->hasGapAfterInstr(miIdx));
|
||||
|
||||
tii->storeRegToStackSlot(*mi->getParent(), nextInstItr, newVReg,
|
||||
true, ss, trc);
|
||||
MachineBasicBlock::iterator storeInstItr(mi);
|
||||
++storeInstItr;
|
||||
MachineInstr *storeInst = &*storeInstItr;
|
||||
unsigned storeInstIdx = miIdx + LiveInterval::InstrSlots::NUM;
|
||||
|
||||
assert(lis->getInstructionFromIndex(storeInstIdx) == 0 &&
|
||||
"Store inst index already in use.");
|
||||
|
||||
lis->InsertMachineInstrInMaps(storeInst, storeInstIdx);
|
||||
|
||||
return storeInstIdx;
|
||||
}
|
||||
|
||||
/// Insert a load of the given veg from the given stack slot immediately
|
||||
/// before the given instruction. Returns the base index of the inserted
|
||||
/// instruction. The caller is responsible for adding an appropriate
|
||||
/// LiveInterval to the LiveIntervals analysis.
|
||||
unsigned insertLoadFor(MachineInstr *mi, unsigned ss,
|
||||
unsigned newVReg,
|
||||
const TargetRegisterClass *trc) {
|
||||
MachineBasicBlock::iterator useInstItr(mi);
|
||||
|
||||
if (!lis->hasGapBeforeInstr(lis->getInstructionIndex(mi))) {
|
||||
lis->scaleNumbering(2);
|
||||
ls->scaleNumbering(2);
|
||||
}
|
||||
|
||||
unsigned miIdx = lis->getInstructionIndex(mi);
|
||||
|
||||
assert(lis->hasGapBeforeInstr(miIdx));
|
||||
|
||||
tii->loadRegFromStackSlot(*mi->getParent(), useInstItr, newVReg, ss, trc);
|
||||
MachineBasicBlock::iterator loadInstItr(mi);
|
||||
--loadInstItr;
|
||||
MachineInstr *loadInst = &*loadInstItr;
|
||||
unsigned loadInstIdx = miIdx - LiveInterval::InstrSlots::NUM;
|
||||
|
||||
assert(lis->getInstructionFromIndex(loadInstIdx) == 0 &&
|
||||
"Load inst index already in use.");
|
||||
|
||||
lis->InsertMachineInstrInMaps(loadInst, loadInstIdx);
|
||||
|
||||
return loadInstIdx;
|
||||
}
|
||||
|
||||
|
||||
/// Add spill ranges for every use/def of the live interval, inserting loads
|
||||
/// immediately before each use, and stores after each def. No folding is
|
||||
/// attempted.
|
||||
std::vector<LiveInterval*> trivialSpillEverywhere(LiveInterval *li) {
|
||||
DOUT << "Spilling everywhere " << *li << "\n";
|
||||
|
||||
assert(li->weight != HUGE_VALF &&
|
||||
"Attempting to spill already spilled value.");
|
||||
@ -51,16 +129,16 @@ public:
|
||||
std::vector<LiveInterval*> added;
|
||||
|
||||
const TargetRegisterClass *trc = mri->getRegClass(li->reg);
|
||||
/*unsigned ss = mfi->CreateStackObject(trc->getSize(),
|
||||
trc->getAlignment());*/
|
||||
unsigned ss = vrm->assignVirt2StackSlot(li->reg);
|
||||
|
||||
MachineRegisterInfo::reg_iterator regItr = mri->reg_begin(li->reg);
|
||||
|
||||
while (regItr != mri->reg_end()) {
|
||||
for (MachineRegisterInfo::reg_iterator
|
||||
regItr = mri->reg_begin(li->reg); regItr != mri->reg_end();) {
|
||||
|
||||
MachineInstr *mi = &*regItr;
|
||||
|
||||
do {
|
||||
++regItr;
|
||||
} while (regItr != mri->reg_end() && (&*regItr == mi));
|
||||
|
||||
SmallVector<unsigned, 2> indices;
|
||||
bool hasUse = false;
|
||||
bool hasDef = false;
|
||||
@ -78,12 +156,12 @@ public:
|
||||
}
|
||||
|
||||
unsigned newVReg = mri->createVirtualRegister(trc);
|
||||
LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
|
||||
newLI->weight = HUGE_VALF;
|
||||
|
||||
vrm->grow();
|
||||
vrm->assignVirt2StackSlot(newVReg, ss);
|
||||
|
||||
LiveInterval *newLI = &lis->getOrCreateInterval(newVReg);
|
||||
newLI->weight = HUGE_VALF;
|
||||
|
||||
for (unsigned i = 0; i < indices.size(); ++i) {
|
||||
mi->getOperand(indices[i]).setReg(newVReg);
|
||||
|
||||
@ -92,6 +170,8 @@ public:
|
||||
}
|
||||
}
|
||||
|
||||
assert(hasUse || hasDef);
|
||||
|
||||
if (hasUse) {
|
||||
unsigned loadInstIdx = insertLoadFor(mi, ss, newVReg, trc);
|
||||
unsigned start = lis->getDefIndex(loadInstIdx),
|
||||
@ -103,7 +183,6 @@ public:
|
||||
LiveRange lr(start, end, vni);
|
||||
|
||||
newLI->addRange(lr);
|
||||
added.push_back(newLI);
|
||||
}
|
||||
|
||||
if (hasDef) {
|
||||
@ -117,90 +196,34 @@ public:
|
||||
LiveRange lr(start, end, vni);
|
||||
|
||||
newLI->addRange(lr);
|
||||
added.push_back(newLI);
|
||||
}
|
||||
|
||||
regItr = mri->reg_begin(li->reg);
|
||||
added.push_back(newLI);
|
||||
}
|
||||
|
||||
|
||||
return added;
|
||||
}
|
||||
|
||||
|
||||
private:
|
||||
|
||||
MachineFunction *mf;
|
||||
LiveIntervals *lis;
|
||||
MachineFrameInfo *mfi;
|
||||
MachineRegisterInfo *mri;
|
||||
const TargetInstrInfo *tii;
|
||||
VirtRegMap *vrm;
|
||||
};
|
||||
|
||||
|
||||
/// Spills any live range using the spill-everywhere method with no attempt at
|
||||
/// folding.
|
||||
class TrivialSpiller : public SpillerBase {
|
||||
public:
|
||||
TrivialSpiller(MachineFunction *mf, LiveIntervals *lis, LiveStacks *ls, VirtRegMap *vrm) :
|
||||
SpillerBase(mf, lis, ls, vrm) {}
|
||||
|
||||
void makeRoomForInsertBefore(MachineInstr *mi) {
|
||||
if (!lis->hasGapBeforeInstr(lis->getInstructionIndex(mi))) {
|
||||
lis->computeNumbering();
|
||||
}
|
||||
|
||||
assert(lis->hasGapBeforeInstr(lis->getInstructionIndex(mi)));
|
||||
}
|
||||
|
||||
unsigned insertStoreFor(MachineInstr *mi, unsigned ss,
|
||||
unsigned newVReg,
|
||||
const TargetRegisterClass *trc) {
|
||||
MachineBasicBlock::iterator nextInstItr(mi);
|
||||
++nextInstItr;
|
||||
|
||||
makeRoomForInsertBefore(&*nextInstItr);
|
||||
|
||||
unsigned miIdx = lis->getInstructionIndex(mi);
|
||||
|
||||
tii->storeRegToStackSlot(*mi->getParent(), nextInstItr, newVReg,
|
||||
true, ss, trc);
|
||||
MachineBasicBlock::iterator storeInstItr(mi);
|
||||
++storeInstItr;
|
||||
MachineInstr *storeInst = &*storeInstItr;
|
||||
unsigned storeInstIdx = miIdx + LiveIntervals::InstrSlots::NUM;
|
||||
|
||||
assert(lis->getInstructionFromIndex(storeInstIdx) == 0 &&
|
||||
"Store inst index already in use.");
|
||||
|
||||
lis->InsertMachineInstrInMaps(storeInst, storeInstIdx);
|
||||
|
||||
return storeInstIdx;
|
||||
}
|
||||
|
||||
unsigned insertLoadFor(MachineInstr *mi, unsigned ss,
|
||||
unsigned newVReg,
|
||||
const TargetRegisterClass *trc) {
|
||||
MachineBasicBlock::iterator useInstItr(mi);
|
||||
|
||||
makeRoomForInsertBefore(mi);
|
||||
|
||||
unsigned miIdx = lis->getInstructionIndex(mi);
|
||||
|
||||
tii->loadRegFromStackSlot(*mi->getParent(), useInstItr, newVReg, ss, trc);
|
||||
MachineBasicBlock::iterator loadInstItr(mi);
|
||||
--loadInstItr;
|
||||
MachineInstr *loadInst = &*loadInstItr;
|
||||
unsigned loadInstIdx = miIdx - LiveIntervals::InstrSlots::NUM;
|
||||
|
||||
assert(lis->getInstructionFromIndex(loadInstIdx) == 0 &&
|
||||
"Load inst index already in use.");
|
||||
|
||||
lis->InsertMachineInstrInMaps(loadInst, loadInstIdx);
|
||||
|
||||
return loadInstIdx;
|
||||
std::vector<LiveInterval*> spill(LiveInterval *li) {
|
||||
return trivialSpillEverywhere(li);
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
|
||||
llvm::Spiller* llvm::createSpiller(MachineFunction *mf, LiveIntervals *lis,
|
||||
VirtRegMap *vrm) {
|
||||
return new TrivialSpiller(mf, lis, vrm);
|
||||
LiveStacks *ls, VirtRegMap *vrm) {
|
||||
return new TrivialSpiller(mf, lis, ls, vrm);
|
||||
}
|
||||
|
@ -13,8 +13,9 @@
|
||||
#include <vector>
|
||||
|
||||
namespace llvm {
|
||||
struct LiveInterval;
|
||||
class LiveInterval;
|
||||
class LiveIntervals;
|
||||
class LiveStacks;
|
||||
class MachineFunction;
|
||||
class VirtRegMap;
|
||||
|
||||
@ -30,7 +31,7 @@ namespace llvm {
|
||||
|
||||
/// Create and return a spiller object, as specified on the command line.
|
||||
Spiller* createSpiller(MachineFunction *mf, LiveIntervals *li,
|
||||
VirtRegMap *vrm);
|
||||
LiveStacks *ls, VirtRegMap *vrm);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
@ -1027,7 +1027,7 @@ bool StrongPHIElimination::runOnMachineFunction(MachineFunction &Fn) {
|
||||
if (MBB != PInstr->getParent() &&
|
||||
InputI.liveAt(LI.getMBBStartIdx(PInstr->getParent())) &&
|
||||
InputI.expiredAt(LI.getInstructionIndex(PInstr) +
|
||||
LiveIntervals::InstrSlots::NUM))
|
||||
LiveInterval::InstrSlots::NUM))
|
||||
InputI.removeRange(LI.getMBBStartIdx(PInstr->getParent()),
|
||||
LI.getInstructionIndex(PInstr),
|
||||
true);
|
||||
|
@ -33,15 +33,16 @@ STATISTIC(NumSUnfold , "Number of stores unfolded");
|
||||
STATISTIC(NumModRefUnfold, "Number of modref unfolded");
|
||||
|
||||
namespace {
|
||||
enum RewriterName { simple, local };
|
||||
enum RewriterName { simple, local, trivial };
|
||||
}
|
||||
|
||||
static cl::opt<RewriterName>
|
||||
RewriterOpt("rewriter",
|
||||
cl::desc("Rewriter to use: (default: local)"),
|
||||
cl::Prefix,
|
||||
cl::values(clEnumVal(simple, "simple rewriter"),
|
||||
clEnumVal(local, "local rewriter"),
|
||||
cl::values(clEnumVal(simple, "simple rewriter"),
|
||||
clEnumVal(local, "local rewriter"),
|
||||
clEnumVal(trivial, "trivial rewriter"),
|
||||
clEnumValEnd),
|
||||
cl::init(local));
|
||||
|
||||
@ -126,6 +127,42 @@ struct VISIBILITY_HIDDEN SimpleRewriter : public VirtRegRewriter {
|
||||
|
||||
};
|
||||
|
||||
/// This class is intended for use with the new spilling framework only. It
|
||||
/// rewrites vreg def/uses to use the assigned preg, but does not insert any
|
||||
/// spill code.
|
||||
struct VISIBILITY_HIDDEN TrivialRewriter : public VirtRegRewriter {
|
||||
|
||||
bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM,
|
||||
LiveIntervals* LIs) {
|
||||
DOUT << "********** REWRITE MACHINE CODE **********\n";
|
||||
DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
|
||||
MachineRegisterInfo *mri = &MF.getRegInfo();
|
||||
|
||||
bool changed = false;
|
||||
|
||||
for (LiveIntervals::iterator liItr = LIs->begin(), liEnd = LIs->end();
|
||||
liItr != liEnd; ++liItr) {
|
||||
|
||||
if (TargetRegisterInfo::isVirtualRegister(liItr->first)) {
|
||||
if (VRM.hasPhys(liItr->first)) {
|
||||
unsigned preg = VRM.getPhys(liItr->first);
|
||||
mri->replaceRegWith(liItr->first, preg);
|
||||
mri->setPhysRegUsed(preg);
|
||||
changed = true;
|
||||
}
|
||||
}
|
||||
else {
|
||||
if (!liItr->second->empty()) {
|
||||
mri->setPhysRegUsed(liItr->first);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return changed;
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
// ************************************************************************ //
|
||||
|
||||
/// AvailableSpills - As the local rewriter is scanning and rewriting an MBB
|
||||
@ -2182,5 +2219,7 @@ llvm::VirtRegRewriter* llvm::createVirtRegRewriter() {
|
||||
return new LocalRewriter();
|
||||
case simple:
|
||||
return new SimpleRewriter();
|
||||
case trivial:
|
||||
return new TrivialRewriter();
|
||||
}
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user