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[Hexagon] Adding DuplexInst instruction format and duplex class defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231828 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -19,9 +19,87 @@
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def TypeMEMOP : IType<9>;
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def TypeNV : IType<10>;
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def TypeDUPLEX : IType<11>;
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def TypeCOMPOUND : IType<12>;
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def TypeAG_VX : IType<28>;
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def TypeAG_VM : IType<29>;
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def TypePREFIX : IType<30>;
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// Duplex Instruction Class Declaration
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//===----------------------------------------------------------------------===//
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class OpcodeDuplex {
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field bits<32> Inst = ?; // Default to an invalid insn.
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bits<4> IClass = 0; // ICLASS
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bits<13> ISubHi = 0; // Low sub-insn
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bits<13> ISubLo = 0; // High sub-insn
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let Inst{31-29} = IClass{3-1};
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let Inst{13} = IClass{0};
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let Inst{15-14} = 0;
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let Inst{28-16} = ISubHi;
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let Inst{12-0} = ISubLo;
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}
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class InstDuplex<bits<4> iClass, list<dag> pattern = [],
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string cstr = "">
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: Instruction, OpcodeDuplex {
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let Namespace = "Hexagon";
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IType Type = TypeDUPLEX; // uses slot 0,1
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let isCodeGenOnly = 1;
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let hasSideEffects = 0;
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dag OutOperandList = (outs);
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dag InOperandList = (ins);
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let IClass = iClass;
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let Constraints = cstr;
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let Itinerary = DUPLEX;
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let Size = 4;
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// SoftFail is a field the disassembler can use to provide a way for
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// instructions to not match without killing the whole decode process. It is
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// mainly used for ARM, but Tablegen expects this field to exist or it fails
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// to build the decode table.
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field bits<32> SoftFail = 0;
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// *** Must match MCTargetDesc/HexagonBaseInfo.h ***
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let TSFlags{4-0} = Type.Value;
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// Predicated instructions.
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bits<1> isPredicated = 0;
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let TSFlags{6} = isPredicated;
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bits<1> isPredicatedFalse = 0;
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let TSFlags{7} = isPredicatedFalse;
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bits<1> isPredicatedNew = 0;
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let TSFlags{8} = isPredicatedNew;
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// New-value insn helper fields.
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bits<1> isNewValue = 0;
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let TSFlags{9} = isNewValue; // New-value consumer insn.
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bits<1> hasNewValue = 0;
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let TSFlags{10} = hasNewValue; // New-value producer insn.
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bits<3> opNewValue = 0;
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let TSFlags{13-11} = opNewValue; // New-value produced operand.
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bits<1> isNVStorable = 0;
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let TSFlags{14} = isNVStorable; // Store that can become new-value store.
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bits<1> isNVStore = 0;
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let TSFlags{15} = isNVStore; // New-value store insn.
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// Immediate extender helper fields.
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bits<1> isExtendable = 0;
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let TSFlags{16} = isExtendable; // Insn may be extended.
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bits<1> isExtended = 0;
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let TSFlags{17} = isExtended; // Insn must be extended.
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bits<3> opExtendable = 0;
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let TSFlags{20-18} = opExtendable; // Which operand may be extended.
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bits<1> isExtentSigned = 0;
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let TSFlags{21} = isExtentSigned; // Signed or unsigned range.
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bits<5> opExtentBits = 0;
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let TSFlags{26-22} = opExtentBits; //Number of bits of range before extending.
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bits<2> opExtentAlign = 0;
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let TSFlags{28-27} = opExtentAlign; // Alignment exponent before extending.
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}
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//----------------------------------------------------------------------------//
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// Instruction Classes Definitions
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//----------------------------------------------------------------------------//
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@ -5741,6 +5741,22 @@ def S2_tableidxh : tableidxRaw<"tableidxh", 0b01>;
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def S2_tableidxw : tableidxRaw<"tableidxw", 0b10>;
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def S2_tableidxd : tableidxRaw<"tableidxd", 0b11>;
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//===----------------------------------------------------------------------===//
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// Template class for 'table index' instructions which are assembler mapped
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// to their :raw format.
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//===----------------------------------------------------------------------===//
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let isPseudo = 1 in
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class tableidx_goodsyntax <string mnemonic>
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: SInst <(outs IntRegs:$Rx),
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(ins IntRegs:$_dst_, IntRegs:$Rs, u4Imm:$u4, u5Imm:$u5),
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"$Rx = "#mnemonic#"($Rs, #$u4, #$u5)",
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[], "$Rx = $_dst_" >;
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def S2_tableidxb_goodsyntax : tableidx_goodsyntax<"tableidxb">;
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def S2_tableidxh_goodsyntax : tableidx_goodsyntax<"tableidxh">;
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def S2_tableidxw_goodsyntax : tableidx_goodsyntax<"tableidxw">;
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def S2_tableidxd_goodsyntax : tableidx_goodsyntax<"tableidxd">;
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//===----------------------------------------------------------------------===//
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// V3 Instructions +
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//===----------------------------------------------------------------------===//
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@ -11,6 +11,25 @@
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//
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//===----------------------------------------------------------------------===//
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def DuplexIClass0: InstDuplex < 0 >;
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def DuplexIClass1: InstDuplex < 1 >;
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def DuplexIClass2: InstDuplex < 2 >;
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let isExtendable = 1 in {
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def DuplexIClass3: InstDuplex < 3 >;
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def DuplexIClass4: InstDuplex < 4 >;
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def DuplexIClass5: InstDuplex < 5 >;
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def DuplexIClass6: InstDuplex < 6 >;
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def DuplexIClass7: InstDuplex < 7 >;
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}
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def DuplexIClass8: InstDuplex < 8 >;
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def DuplexIClass9: InstDuplex < 9 >;
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def DuplexIClassA: InstDuplex < 0xA >;
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def DuplexIClassB: InstDuplex < 0xB >;
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def DuplexIClassC: InstDuplex < 0xC >;
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def DuplexIClassD: InstDuplex < 0xD >;
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def DuplexIClassE: InstDuplex < 0xE >;
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def DuplexIClassF: InstDuplex < 0xF >;
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def addrga: PatLeaf<(i32 AddrGA:$Addr)>;
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def addrgp: PatLeaf<(i32 AddrGP:$Addr)>;
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