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R600/SI: Determine target-specific encoding of READLANE and WRITELANE early v2

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These are VOP2 on SI and VOP3 on VI, and their pseudos are neither, which can
be a problem. In order to make isVOP2 and isVOP3 queries behave as expected,
the encoding must be determined first.

This doesn't fix any known issue, but better safe than sorry.

v2: add and use getMCOpcodeFromPseudo

Tested-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227987 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Marek Olsak
2015-02-03 17:37:57 +00:00
parent b19dbd9eb3
commit f426f1db6e
2 changed files with 12 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
lib/Target/R600/AMDGPUInstrInfo.h
View File

@@ -140,6 +140,12 @@ public:
/// not exist. If Opcode is not a pseudo instruction, this is identity. /// not exist. If Opcode is not a pseudo instruction, this is identity.
int pseudoToMCOpcode(int Opcode) const; int pseudoToMCOpcode(int Opcode) const;
/// \brief Return the descriptor of the target-specific machine instruction
/// that corresponds to the specified pseudo or native opcode.
const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
return get(pseudoToMCOpcode(Opcode));
}
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
// Pure virtual funtions to be implemented by sub-classes. // Pure virtual funtions to be implemented by sub-classes.
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//

8
lib/Target/R600/SIRegisterInfo.cpp
View File

@@ -204,7 +204,9 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
Ctx.emitError("Ran out of VGPRs for spilling SGPR"); Ctx.emitError("Ran out of VGPRs for spilling SGPR");
} }
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_WRITELANE_B32), Spill.VGPR) BuildMI(*MBB, MI, DL,
TII->getMCOpcodeFromPseudo(AMDGPU::V_WRITELANE_B32),
Spill.VGPR)
.addReg(SubReg) .addReg(SubReg)
.addImm(Spill.Lane); .addImm(Spill.Lane);
@@ -236,7 +238,9 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
if (isM0) if (isM0)
SubReg = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0); SubReg = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0);
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READLANE_B32), SubReg) BuildMI(*MBB, MI, DL,
TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32),
SubReg)
.addReg(Spill.VGPR) .addReg(Spill.VGPR)
.addImm(Spill.Lane) .addImm(Spill.Lane)
.addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine); .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);