mirror of
https://github.com/c64scene-ar/llvm-6502.git
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More refactoring of basic SSE arith instructions. Open room for 256-bit instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108204 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
314451326a
commit
f428fee70d
@ -393,75 +393,103 @@ let Uses = [EFLAGS], usesCustomInserter = 1 in {
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/// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
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multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
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RegisterClass RC, X86MemOperand x86memop> {
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RegisterClass RC, X86MemOperand x86memop,
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bit Is2Addr = 1> {
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let isCommutable = 1 in {
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def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
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OpcodeStr, [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
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}
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def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
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OpcodeStr, [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
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}
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/// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
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multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
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string asm, string SSEVer, string FPSizeStr,
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Operand memopr, ComplexPattern mem_cpat> {
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string asm, string SSEVer, string FPSizeStr,
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Operand memopr, ComplexPattern mem_cpat,
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bit Is2Addr = 1> {
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def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
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asm, [(set RC:$dst, (
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!nameconcat<Intrinsic>("int_x86_sse",
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!strconcat(SSEVer, !strconcat("_",
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!strconcat(OpcodeStr, FPSizeStr))))
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RC:$src1, RC:$src2))]>;
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!if(Is2Addr,
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!strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_sse",
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!strconcat(SSEVer, !strconcat("_",
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!strconcat(OpcodeStr, FPSizeStr))))
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RC:$src1, RC:$src2))]>;
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def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
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asm, [(set RC:$dst, (
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!nameconcat<Intrinsic>("int_x86_sse",
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!strconcat(SSEVer, !strconcat("_",
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!strconcat(OpcodeStr, FPSizeStr))))
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RC:$src1, mem_cpat:$src2))]>;
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!if(Is2Addr,
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!strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_sse",
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!strconcat(SSEVer, !strconcat("_",
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!strconcat(OpcodeStr, FPSizeStr))))
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RC:$src1, mem_cpat:$src2))]>;
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}
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/// sse12_fp_packed - SSE 1 & 2 packed instructions class
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multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
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RegisterClass RC, ValueType vt,
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X86MemOperand x86memop, PatFrag mem_frag,
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Domain d, bit MayLoad = 0> {
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Domain d, bit Is2Addr = 1> {
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let isCommutable = 1 in
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def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
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OpcodeStr, [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))],d>;
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let mayLoad = MayLoad in
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
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let mayLoad = 1 in
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def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
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OpcodeStr, [(set RC:$dst, (OpNode RC:$src1,
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(mem_frag addr:$src2)))],d>;
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
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}
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/// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
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multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
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string OpcodeStr, X86MemOperand x86memop,
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list<dag> pat_rr, list<dag> pat_rm> {
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list<dag> pat_rr, list<dag> pat_rm,
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bit Is2Addr = 1> {
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let isCommutable = 1 in
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def rr : PI<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2), OpcodeStr, pat_rr, d>;
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def rm : PI<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, x86memop:$src2), OpcodeStr, pat_rm, d>;
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def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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pat_rr, d>;
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def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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pat_rm, d>;
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}
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/// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
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multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
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string asm, string SSEVer, string FPSizeStr,
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X86MemOperand x86memop, PatFrag mem_frag,
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Domain d> {
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string asm, string SSEVer, string FPSizeStr,
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X86MemOperand x86memop, PatFrag mem_frag,
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Domain d, bit Is2Addr = 1> {
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def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
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asm, [(set RC:$dst, (
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!nameconcat<Intrinsic>("int_x86_sse",
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!strconcat(SSEVer, !strconcat("_",
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!strconcat(OpcodeStr, FPSizeStr))))
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RC:$src1, RC:$src2))], d>;
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def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
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asm, [(set RC:$dst, (
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!nameconcat<Intrinsic>("int_x86_sse",
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!strconcat(SSEVer, !strconcat("_",
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!strconcat(OpcodeStr, FPSizeStr))))
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RC:$src1, (mem_frag addr:$src2)))], d>;
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!if(Is2Addr,
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!strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_sse",
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!strconcat(SSEVer, !strconcat("_",
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!strconcat(OpcodeStr, FPSizeStr))))
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RC:$src1, RC:$src2))], d>;
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def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
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!if(Is2Addr,
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!strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_sse",
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!strconcat(SSEVer, !strconcat("_",
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!strconcat(OpcodeStr, FPSizeStr))))
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RC:$src1, (mem_frag addr:$src2)))], d>;
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}
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//===----------------------------------------------------------------------===//
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@ -1652,36 +1680,33 @@ def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
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/// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
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///
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multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
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SDNode OpNode, bit MayLoad = 0> {
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SDNode OpNode> {
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let isAsmParserOnly = 1 in {
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defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
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"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode, FR32,
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f32, f128mem, memopfsf32, SSEPackedSingle, MayLoad>, VEX_4V;
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defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
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FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, VEX_4V;
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defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
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"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode, FR64,
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f64, f128mem, memopfsf64, SSEPackedDouble, MayLoad>, OpSize,
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VEX_4V;
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defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
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FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, OpSize, VEX_4V;
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}
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let Constraints = "$src1 = $dst" in {
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defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
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"ps\t{$src2, $dst|$dst, $src2}"), OpNode, FR32, f32,
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f128mem, memopfsf32, SSEPackedSingle, MayLoad>, TB;
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defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
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f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
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defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
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"pd\t{$src2, $dst|$dst, $src2}"), OpNode, FR64, f64,
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f128mem, memopfsf64, SSEPackedDouble, MayLoad>, TB, OpSize;
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defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
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f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
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}
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}
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// Alias bitwise logical operations using SSE logical ops on packed FP values.
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defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
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defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
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defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
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let mayLoad = 0 in {
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defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
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defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
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defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
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}
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let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
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defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef, 1>;
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defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
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/// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
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///
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@ -1690,31 +1715,29 @@ multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
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list<list<dag>> Pattern = []> {
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let isAsmParserOnly = 1 in {
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defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
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!strconcat(OpcodeStr, "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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f128mem,
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!strconcat(OpcodeStr, "ps"), f128mem,
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!if(HasPat, Pattern[0], // rr
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[(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
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VR128:$src2)))]),
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!if(HasPat, Pattern[2], // rm
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[(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
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(memopv2i64 addr:$src2)))])>,
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(memopv2i64 addr:$src2)))]), 0>,
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VEX_4V;
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defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
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!strconcat(OpcodeStr, "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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f128mem,
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!strconcat(OpcodeStr, "pd"), f128mem,
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!if(HasPat, Pattern[1], // rr
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[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
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(bc_v2i64 (v2f64
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VR128:$src2))))]),
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!if(HasPat, Pattern[3], // rm
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[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
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(memopv2i64 addr:$src2)))])>,
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(memopv2i64 addr:$src2)))]), 0>,
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OpSize, VEX_4V;
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}
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let Constraints = "$src1 = $dst" in {
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defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
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!strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"), f128mem,
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!strconcat(OpcodeStr, "ps"), f128mem,
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!if(HasPat, Pattern[0], // rr
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[(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
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VR128:$src2)))]),
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@ -1723,7 +1746,7 @@ multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
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(memopv2i64 addr:$src2)))])>, TB;
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defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
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!strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"), f128mem,
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!strconcat(OpcodeStr, "pd"), f128mem,
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!if(HasPat, Pattern[1], // rr
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[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
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(bc_v2i64 (v2f64
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@ -1759,7 +1782,7 @@ let isCommutable = 0 in
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// SSE 1 & 2 - Arithmetic Instructions
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//===----------------------------------------------------------------------===//
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/// basic_sse12_fp_binop_rm - SSE 1 & 2 binops come in both scalar and
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/// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
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/// vector forms.
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///
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/// In addition, we also have a special variant of the scalar form here to
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@ -1769,158 +1792,86 @@ let isCommutable = 0 in
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///
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/// These three forms can each be reg+reg or reg+mem.
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///
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multiclass basic_sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
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SDNode OpNode> {
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multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
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bit Is2Addr = 1> {
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defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
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OpNode, FR32, f32mem, Is2Addr>, XS;
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defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
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OpNode, FR64, f64mem, Is2Addr>, XD;
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}
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let isAsmParserOnly = 1 in {
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defm V#NAME#SS : sse12_fp_scalar<opc,
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!strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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OpNode, FR32, f32mem>, XS, VEX_4V;
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defm V#NAME#SD : sse12_fp_scalar<opc,
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!strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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OpNode, FR64, f64mem>, XD, VEX_4V;
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defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
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"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
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VR128, v4f32, f128mem, memopv4f32, SSEPackedSingle>,
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VEX_4V;
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defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
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"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
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VR128, v2f64, f128mem, memopv2f64, SSEPackedDouble>,
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OpSize, VEX_4V;
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defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
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!strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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"", "_ss", ssmem, sse_load_f32>, XS, VEX_4V;
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defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
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!strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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"2", "_sd", sdmem, sse_load_f64>, XD, VEX_4V;
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multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
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bit Is2Addr = 1> {
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let mayLoad = 0 in {
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defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
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v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
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defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
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v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
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}
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}
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let Constraints = "$src1 = $dst" in {
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defm SS : sse12_fp_scalar<opc,
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!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
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OpNode, FR32, f32mem>, XS;
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multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
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bit Is2Addr = 1> {
|
||||
defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
|
||||
!strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
|
||||
defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
|
||||
!strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
|
||||
}
|
||||
|
||||
defm SD : sse12_fp_scalar<opc,
|
||||
!strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
|
||||
OpNode, FR64, f64mem>, XD;
|
||||
multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
|
||||
bit Is2Addr = 1> {
|
||||
defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
|
||||
!strconcat(OpcodeStr, "ps"), "", "_ps", f128mem, memopv4f32,
|
||||
SSEPackedSingle, Is2Addr>, TB;
|
||||
|
||||
defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
|
||||
"ps\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v4f32,
|
||||
f128mem, memopv4f32, SSEPackedSingle>, TB;
|
||||
|
||||
defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
|
||||
"pd\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v2f64,
|
||||
f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
|
||||
|
||||
defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
|
||||
!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
|
||||
"", "_ss", ssmem, sse_load_f32>, XS;
|
||||
|
||||
defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
|
||||
!strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
|
||||
"2", "_sd", sdmem, sse_load_f64>, XD;
|
||||
}
|
||||
defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
|
||||
!strconcat(OpcodeStr, "pd"), "2", "_pd", f128mem, memopv2f64,
|
||||
SSEPackedDouble, Is2Addr>, TB, OpSize;
|
||||
}
|
||||
|
||||
// Arithmetic instructions
|
||||
defm ADD : basic_sse12_fp_binop_rm<0x58, "add", fadd>;
|
||||
defm MUL : basic_sse12_fp_binop_rm<0x59, "mul", fmul>;
|
||||
let isAsmParserOnly = 1, Predicates = [HasAVX] in {
|
||||
defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
|
||||
basic_sse12_fp_binop_p<0x58, "add", fadd, 0>, VEX_4V;
|
||||
defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
|
||||
basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>, VEX_4V;
|
||||
|
||||
let isCommutable = 0 in {
|
||||
defm SUB : basic_sse12_fp_binop_rm<0x5C, "sub", fsub>;
|
||||
defm DIV : basic_sse12_fp_binop_rm<0x5E, "div", fdiv>;
|
||||
}
|
||||
|
||||
/// sse12_fp_binop_rm - Other SSE 1 & 2 binops
|
||||
///
|
||||
/// This multiclass is like basic_sse12_fp_binop_rm, with the addition of
|
||||
/// instructions for a full-vector intrinsic form. Operations that map
|
||||
/// onto C operators don't use this form since they just use the plain
|
||||
/// vector form instead of having a separate vector intrinsic form.
|
||||
///
|
||||
multiclass sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
|
||||
SDNode OpNode> {
|
||||
|
||||
let isAsmParserOnly = 1 in {
|
||||
// Scalar operation, reg+reg.
|
||||
defm V#NAME#SS : sse12_fp_scalar<opc,
|
||||
!strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
||||
OpNode, FR32, f32mem>, XS, VEX_4V;
|
||||
|
||||
defm V#NAME#SD : sse12_fp_scalar<opc,
|
||||
!strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
||||
OpNode, FR64, f64mem>, XD, VEX_4V;
|
||||
|
||||
defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
|
||||
"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
|
||||
VR128, v4f32, f128mem, memopv4f32, SSEPackedSingle>,
|
||||
VEX_4V;
|
||||
|
||||
defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
|
||||
"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
|
||||
VR128, v2f64, f128mem, memopv2f64, SSEPackedDouble>,
|
||||
OpSize, VEX_4V;
|
||||
|
||||
defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
|
||||
!strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
||||
"", "_ss", ssmem, sse_load_f32>, XS, VEX_4V;
|
||||
|
||||
defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
|
||||
!strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
||||
"2", "_sd", sdmem, sse_load_f64>, XD, VEX_4V;
|
||||
|
||||
defm V#NAME#PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
|
||||
!strconcat(OpcodeStr, "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
||||
"", "_ps", f128mem, memopv4f32, SSEPackedSingle>, VEX_4V;
|
||||
|
||||
defm V#NAME#PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
|
||||
!strconcat(OpcodeStr, "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
||||
"2", "_pd", f128mem, memopv2f64, SSEPackedDouble>, OpSize,
|
||||
VEX_4V;
|
||||
}
|
||||
|
||||
let Constraints = "$src1 = $dst" in {
|
||||
// Scalar operation, reg+reg.
|
||||
defm SS : sse12_fp_scalar<opc,
|
||||
!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
|
||||
OpNode, FR32, f32mem>, XS;
|
||||
defm SD : sse12_fp_scalar<opc,
|
||||
!strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
|
||||
OpNode, FR64, f64mem>, XD;
|
||||
defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
|
||||
"ps\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v4f32,
|
||||
f128mem, memopv4f32, SSEPackedSingle>, TB;
|
||||
|
||||
defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
|
||||
"pd\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v2f64,
|
||||
f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
|
||||
|
||||
defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
|
||||
!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
|
||||
"", "_ss", ssmem, sse_load_f32>, XS;
|
||||
|
||||
defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
|
||||
!strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
|
||||
"2", "_sd", sdmem, sse_load_f64>, XD;
|
||||
|
||||
defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
|
||||
!strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
|
||||
"", "_ps", f128mem, memopv4f32, SSEPackedSingle>, TB;
|
||||
|
||||
defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
|
||||
!strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
|
||||
"2", "_pd", f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
|
||||
let isCommutable = 0 in {
|
||||
defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
|
||||
basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>, VEX_4V;
|
||||
defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
|
||||
basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>, VEX_4V;
|
||||
defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
|
||||
basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>, VEX_4V;
|
||||
defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
|
||||
basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>, VEX_4V;
|
||||
}
|
||||
}
|
||||
|
||||
let isCommutable = 0 in {
|
||||
defm MAX : sse12_fp_binop_rm<0x5F, "max", X86fmax>;
|
||||
defm MIN : sse12_fp_binop_rm<0x5D, "min", X86fmin>;
|
||||
let Constraints = "$src1 = $dst" in {
|
||||
defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
|
||||
basic_sse12_fp_binop_p<0x58, "add", fadd>,
|
||||
basic_sse12_fp_binop_s_int<0x58, "add">;
|
||||
defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
|
||||
basic_sse12_fp_binop_p<0x59, "mul", fmul>,
|
||||
basic_sse12_fp_binop_s_int<0x59, "mul">;
|
||||
|
||||
let isCommutable = 0 in {
|
||||
defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
|
||||
basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
|
||||
basic_sse12_fp_binop_s_int<0x5C, "sub">;
|
||||
defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
|
||||
basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
|
||||
basic_sse12_fp_binop_s_int<0x5E, "div">;
|
||||
defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
|
||||
basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
|
||||
basic_sse12_fp_binop_s_int<0x5F, "max">,
|
||||
basic_sse12_fp_binop_p_int<0x5F, "max">;
|
||||
defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
|
||||
basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
|
||||
basic_sse12_fp_binop_s_int<0x5D, "min">,
|
||||
basic_sse12_fp_binop_p_int<0x5D, "min">;
|
||||
}
|
||||
}
|
||||
|
||||
/// Unop Arithmetic
|
||||
|
||||
Loading…
Reference in New Issue
Block a user