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Switch MachineTraceMetrics to the new TargetSchedModel interface.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165235 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-10-04 17:30:40 +00:00
parent e37091931c
commit f43fe1d163
3 changed files with 28 additions and 32 deletions
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1
include/llvm/CodeGen/TargetSchedule.h
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@ -63,6 +63,7 @@ public:
bool FindMin) const; bool FindMin) const;
unsigned getProcessorID() const { return SchedModel.getProcessorID(); } unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
private: private:
/// getDefLatency is a helper for computeOperandLatency. Return the /// getDefLatency is a helper for computeOperandLatency. Return the

56
lib/CodeGen/MachineTraceMetrics.cpp
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@ -14,9 +14,10 @@
#include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/Passes.h"
#include "llvm/MC/MCInstrItineraries.h" #include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/PostOrderIterator.h" #include "llvm/ADT/PostOrderIterator.h"
@ -50,9 +51,11 @@ bool MachineTraceMetrics::runOnMachineFunction(MachineFunction &Func) {
MF = &Func; MF = &Func;
TII = MF->getTarget().getInstrInfo(); TII = MF->getTarget().getInstrInfo();
TRI = MF->getTarget().getRegisterInfo(); TRI = MF->getTarget().getRegisterInfo();
ItinData = MF->getTarget().getInstrItineraryData();
MRI = &MF->getRegInfo(); MRI = &MF->getRegInfo();
Loops = &getAnalysis<MachineLoopInfo>(); Loops = &getAnalysis<MachineLoopInfo>();
const TargetSubtargetInfo &ST =
MF->getTarget().getSubtarget<TargetSubtargetInfo>();
SchedModel.init(*ST.getSchedModel(), &ST, TII);
BlockInfo.resize(MF->getNumBlockIDs()); BlockInfo.resize(MF->getNumBlockIDs());
return false; return false;
} }
@ -743,10 +746,9 @@ computeInstrDepths(const MachineBasicBlock *MBB) {
unsigned DepCycle = Cycles.lookup(Dep.DefMI).Depth; unsigned DepCycle = Cycles.lookup(Dep.DefMI).Depth;
// Add latency if DefMI is a real instruction. Transients get latency 0. // Add latency if DefMI is a real instruction. Transients get latency 0.
if (!Dep.DefMI->isTransient()) if (!Dep.DefMI->isTransient())
DepCycle += MTM.TII->computeOperandLatency(MTM.ItinData, DepCycle += MTM.SchedModel
Dep.DefMI, Dep.DefOp, .computeOperandLatency(Dep.DefMI, Dep.DefOp, UseMI, Dep.UseOp,
UseMI, Dep.UseOp, /* FindMin = */ false);
/* FindMin = */ false);
Cycle = std::max(Cycle, DepCycle); Cycle = std::max(Cycle, DepCycle);
} }
// Remember the instruction depth. // Remember the instruction depth.
@ -769,7 +771,7 @@ computeInstrDepths(const MachineBasicBlock *MBB) {
// Height is the issue height computed from virtual register dependencies alone. // Height is the issue height computed from virtual register dependencies alone.
static unsigned updatePhysDepsUpwards(const MachineInstr *MI, unsigned Height, static unsigned updatePhysDepsUpwards(const MachineInstr *MI, unsigned Height,
SparseSet<LiveRegUnit> &RegUnits, SparseSet<LiveRegUnit> &RegUnits,
const InstrItineraryData *ItinData, const TargetSchedModel &SchedModel,
const TargetInstrInfo *TII, const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI) { const TargetRegisterInfo *TRI) {
SmallVector<unsigned, 8> ReadOps; SmallVector<unsigned, 8> ReadOps;
@ -792,14 +794,10 @@ static unsigned updatePhysDepsUpwards(const MachineInstr *MI, unsigned Height,
unsigned DepHeight = I->Cycle; unsigned DepHeight = I->Cycle;
if (!MI->isTransient()) { if (!MI->isTransient()) {
// We may not know the UseMI of this dependency, if it came from the // We may not know the UseMI of this dependency, if it came from the
// live-in list. // live-in list. SchedModel can handle a NULL UseMI.
if (I->MI) DepHeight += SchedModel
DepHeight += TII->computeOperandLatency(ItinData, .computeOperandLatency(MI, MO.getOperandNo(), I->MI, I->Op,
MI, MO.getOperandNo(), /* FindMin = */ false);
I->MI, I->Op);
else
// No UseMI. Just use the MI latency instead.
DepHeight += TII->getInstrLatency(ItinData, MI);
} }
Height = std::max(Height, DepHeight); Height = std::max(Height, DepHeight);
// This regunit is dead above MI. // This regunit is dead above MI.
@ -832,12 +830,12 @@ typedef DenseMap<const MachineInstr *, unsigned> MIHeightMap;
static bool pushDepHeight(const DataDep &Dep, static bool pushDepHeight(const DataDep &Dep,
const MachineInstr *UseMI, unsigned UseHeight, const MachineInstr *UseMI, unsigned UseHeight,
MIHeightMap &Heights, MIHeightMap &Heights,
const InstrItineraryData *ItinData, const TargetSchedModel &SchedModel,
const TargetInstrInfo *TII) { const TargetInstrInfo *TII) {
// Adjust height by Dep.DefMI latency. // Adjust height by Dep.DefMI latency.
if (!Dep.DefMI->isTransient()) if (!Dep.DefMI->isTransient())
UseHeight += TII->computeOperandLatency(ItinData, Dep.DefMI, Dep.DefOp, UseHeight += SchedModel.computeOperandLatency(Dep.DefMI, Dep.DefOp,
UseMI, Dep.UseOp); UseMI, Dep.UseOp, false);
// Update Heights[DefMI] to be the maximum height seen. // Update Heights[DefMI] to be the maximum height seen.
MIHeightMap::iterator I; MIHeightMap::iterator I;
@ -951,7 +949,7 @@ computeInstrHeights(const MachineBasicBlock *MBB) {
unsigned Height = TBI.Succ ? Cycles.lookup(PHI).Height : 0; unsigned Height = TBI.Succ ? Cycles.lookup(PHI).Height : 0;
DEBUG(dbgs() << "pred\t" << Height << '\t' << *PHI); DEBUG(dbgs() << "pred\t" << Height << '\t' << *PHI);
if (pushDepHeight(Deps.front(), PHI, Height, if (pushDepHeight(Deps.front(), PHI, Height,
Heights, MTM.ItinData, MTM.TII)) Heights, MTM.SchedModel, MTM.TII))
addLiveIns(Deps.front().DefMI, Stack); addLiveIns(Deps.front().DefMI, Stack);
} }
} }
@ -980,11 +978,11 @@ computeInstrHeights(const MachineBasicBlock *MBB) {
// There may also be regunit dependencies to include in the height. // There may also be regunit dependencies to include in the height.
if (HasPhysRegs) if (HasPhysRegs)
Cycle = updatePhysDepsUpwards(MI, Cycle, RegUnits, Cycle = updatePhysDepsUpwards(MI, Cycle, RegUnits,
MTM.ItinData, MTM.TII, MTM.TRI); MTM.SchedModel, MTM.TII, MTM.TRI);
// Update the required height of any virtual registers read by MI. // Update the required height of any virtual registers read by MI.
for (unsigned i = 0, e = Deps.size(); i != e; ++i) for (unsigned i = 0, e = Deps.size(); i != e; ++i)
if (pushDepHeight(Deps[i], MI, Cycle, Heights, MTM.ItinData, MTM.TII)) if (pushDepHeight(Deps[i], MI, Cycle, Heights, MTM.SchedModel, MTM.TII))
addLiveIns(Deps[i].DefMI, Stack); addLiveIns(Deps[i].DefMI, Stack);
InstrCycles &MICycles = Cycles[MI]; InstrCycles &MICycles = Cycles[MI];
@ -1054,10 +1052,8 @@ MachineTraceMetrics::Trace::getPHIDepth(const MachineInstr *PHI) const {
unsigned DepCycle = getInstrCycles(Dep.DefMI).Depth; unsigned DepCycle = getInstrCycles(Dep.DefMI).Depth;
// Add latency if DefMI is a real instruction. Transients get latency 0. // Add latency if DefMI is a real instruction. Transients get latency 0.
if (!Dep.DefMI->isTransient()) if (!Dep.DefMI->isTransient())
DepCycle += TE.MTM.TII->computeOperandLatency(TE.MTM.ItinData, DepCycle += TE.MTM.SchedModel
Dep.DefMI, Dep.DefOp, .computeOperandLatency(Dep.DefMI, Dep.DefOp, PHI, Dep.UseOp, false);
PHI, Dep.UseOp,
/* FindMin = */ false);
return DepCycle; return DepCycle;
} }
@ -1068,9 +1064,8 @@ unsigned MachineTraceMetrics::Trace::getResourceDepth(bool Bottom) const {
unsigned Instrs = TBI.InstrDepth; unsigned Instrs = TBI.InstrDepth;
if (Bottom) if (Bottom)
Instrs += TE.MTM.BlockInfo[getBlockNum()].InstrCount; Instrs += TE.MTM.BlockInfo[getBlockNum()].InstrCount;
if (const MCSchedModel *Model = TE.MTM.ItinData->SchedModel) if (unsigned IW = TE.MTM.SchedModel.getIssueWidth())
if (Model->IssueWidth != 0) Instrs /= IW;
return Instrs / Model->IssueWidth;
// Assume issue width 1 without a schedule model. // Assume issue width 1 without a schedule model.
return Instrs; return Instrs;
} }
@ -1080,9 +1075,8 @@ getResourceLength(ArrayRef<const MachineBasicBlock*> Extrablocks) const {
unsigned Instrs = TBI.InstrDepth + TBI.InstrHeight; unsigned Instrs = TBI.InstrDepth + TBI.InstrHeight;
for (unsigned i = 0, e = Extrablocks.size(); i != e; ++i) for (unsigned i = 0, e = Extrablocks.size(); i != e; ++i)
Instrs += TE.MTM.getResources(Extrablocks[i])->InstrCount; Instrs += TE.MTM.getResources(Extrablocks[i])->InstrCount;
if (const MCSchedModel *Model = TE.MTM.ItinData->SchedModel) if (unsigned IW = TE.MTM.SchedModel.getIssueWidth())
if (Model->IssueWidth != 0) Instrs /= IW;
return Instrs / Model->IssueWidth;
// Assume issue width 1 without a schedule model. // Assume issue width 1 without a schedule model.
return Instrs; return Instrs;
} }

3
lib/CodeGen/MachineTraceMetrics.h
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@ -50,6 +50,7 @@
#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DenseMap.h"
#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/TargetSchedule.h"
namespace llvm { namespace llvm {
@ -67,9 +68,9 @@ class MachineTraceMetrics : public MachineFunctionPass {
const MachineFunction *MF; const MachineFunction *MF;
const TargetInstrInfo *TII; const TargetInstrInfo *TII;
const TargetRegisterInfo *TRI; const TargetRegisterInfo *TRI;
const InstrItineraryData *ItinData;
const MachineRegisterInfo *MRI; const MachineRegisterInfo *MRI;
const MachineLoopInfo *Loops; const MachineLoopInfo *Loops;
TargetSchedModel SchedModel;
public: public:
class Ensemble; class Ensemble;