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ARM assembly parsing and encoding for SSAT16 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136006 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -543,10 +543,20 @@ def imm1_32_XFORM: SDNodeXForm<imm, [{
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def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
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def imm1_32 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 32; }],
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imm1_32_XFORM> {
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let PrintMethod = "printImm1_32Operand";
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let PrintMethod = "printImmPlusOneOperand";
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let ParserMatchClass = Imm1_32AsmOperand;
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}
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def imm1_16_XFORM: SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
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}]>;
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def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
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def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
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imm1_16_XFORM> {
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let PrintMethod = "printImmPlusOneOperand";
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let ParserMatchClass = Imm1_16AsmOperand;
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}
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// Define ARM specific addressing modes.
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// addrmode_imm12 := reg +/- imm12
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//
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@ -2709,7 +2719,7 @@ def SSAT : AI<(outs GPR:$Rd), (ins imm1_32:$sat_imm, GPR:$Rn, shift_imm:$sh),
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let Inst{3-0} = Rn;
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}
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def SSAT16 : AI<(outs GPR:$Rd), (ins imm1_32:$sat_imm, GPR:$Rn), SatFrm,
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def SSAT16 : AI<(outs GPR:$Rd), (ins imm1_16:$sat_imm, GPR:$Rn), SatFrm,
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NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
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bits<4> Rd;
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bits<4> sat_imm;
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@ -1935,7 +1935,7 @@ def t2SSAT: T2SatI<
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}
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def t2SSAT16: T2SatI<
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(outs rGPR:$Rd), (ins imm1_32:$sat_imm, rGPR:$Rn), NoItinerary,
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(outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
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"ssat16", "\t$Rd, $sat_imm, $Rn",
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[/* For disassembly only; pattern left blank */]>,
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Requires<[IsThumb2, HasThumb2DSP]> {
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@ -433,6 +433,14 @@ public:
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int64_t Value = CE->getValue();
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return Value >= 0 && Value < 32;
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}
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bool isImm1_16() const {
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if (Kind != Immediate)
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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int64_t Value = CE->getValue();
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return Value > 0 && Value < 17;
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}
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bool isImm1_32() const {
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if (Kind != Immediate)
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return false;
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@ -704,6 +712,14 @@ public:
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addExpr(Inst, getImm());
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}
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void addImm1_16Operands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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// The constant encodes as the immediate-1, and we store in the instruction
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// the bits as encoded, so subtract off one here.
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
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}
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void addImm1_32Operands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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// The constant encodes as the immediate-1, and we store in the instruction
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@ -830,8 +830,8 @@ void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
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O << "#0x" << utohexstr(Val);
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}
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void ARMInstPrinter::printImm1_32Operand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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unsigned Imm = MI->getOperand(OpNum).getImm();
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O << "#" << Imm + 1;
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}
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@ -114,7 +114,7 @@ public:
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void printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printNEONModImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printImm1_32Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printPCLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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};
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@ -1631,6 +1631,17 @@ _func:
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@ CHECK: ssat r8, #1, r10, asr #32 @ encoding: [0x5a,0x80,0xa0,0xe6]
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@ CHECK: ssat r8, #1, r10, asr #1 @ encoding: [0xda,0x80,0xa0,0xe6]
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@------------------------------------------------------------------------------
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@ SSAT16
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@------------------------------------------------------------------------------
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ssat16 r2, #1, r7
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ssat16 r3, #16, r5
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@ CHECK: ssat16 r2, #1, r7 @ encoding: [0x37,0x2f,0xa0,0xe6]
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@ CHECK: ssat16 r3, #16, r5 @ encoding: [0x35,0x3f,0xaf,0xe6]
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@------------------------------------------------------------------------------
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@ STM*
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@------------------------------------------------------------------------------
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@ -200,3 +200,14 @@
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@ CHECK: error: shift amount must be an immediate
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@ CHECK: ssat r8, #1, r10, lsl #fred
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@ CHECK: ^
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@ Out of range immediates for SSAT16
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ssat16 r2, #0, r7
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ssat16 r3, #17, r5
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@ CHECK: error: invalid operand for instruction
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@ CHECK: ssat16 r2, #0, r7
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@ CHECK: ^
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@ CHECK: error: invalid operand for instruction
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@ CHECK: ssat16 r3, #17, r5
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@ CHECK: ^
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@ -587,6 +587,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
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IMM("neg_zero");
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IMM("imm0_31");
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IMM("imm0_31_m1");
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IMM("imm1_16");
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IMM("imm1_32");
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IMM("nModImm");
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IMM("imm0_7");
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