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Fix the encoding of the armv7m (MClass) for MSR registers other than aspr,

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iaspr, espr and xpsr which also needed to have 0b10 in their mask encoding bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158560 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Enderby 2012-06-15 22:14:44 +00:00
parent 307473dec0
commit f49a4092bc
3 changed files with 41 additions and 31 deletions
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22
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -3354,22 +3354,22 @@ parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
.Case("xpsr_nzcvq", 0x803)
.Case("xpsr_g", 0x403)
.Case("xpsr_nzcvqg", 0xc03)
.Case("ipsr", 5)
.Case("epsr", 6)
.Case("iepsr", 7)
.Case("msp", 8)
.Case("psp", 9)
.Case("primask", 16)
.Case("basepri", 17)
.Case("basepri_max", 18)
.Case("faultmask", 19)
.Case("control", 20)
.Case("ipsr", 0x805)
.Case("epsr", 0x806)
.Case("iepsr", 0x807)
.Case("msp", 0x808)
.Case("psp", 0x809)
.Case("primask", 0x810)
.Case("basepri", 0x811)
.Case("basepri_max", 0x812)
.Case("faultmask", 0x813)
.Case("control", 0x814)
.Default(~0U);
if (FlagsVal == ~0U)
return MatchOperand_NoMatch;
if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19)
if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
// basepri, basepri_max and faultmask only valid for V7m.
return MatchOperand_NoMatch;

30
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
View File

@ -671,16 +671,26 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
case 0x803: O << "xpsr"; return; // with _nzcvq bits is an alias for xpsr
case 0x403: O << "xpsr_g"; return;
case 0xc03: O << "xpsr_nzcvqg"; return;
case 5: O << "ipsr"; return;
case 6: O << "epsr"; return;
case 7: O << "iepsr"; return;
case 8: O << "msp"; return;
case 9: O << "psp"; return;
case 16: O << "primask"; return;
case 17: O << "basepri"; return;
case 18: O << "basepri_max"; return;
case 19: O << "faultmask"; return;
case 20: O << "control"; return;
case 5:
case 0x805: O << "ipsr"; return;
case 6:
case 0x806: O << "epsr"; return;
case 7:
case 0x807: O << "iepsr"; return;
case 8:
case 0x808: O << "msp"; return;
case 9:
case 0x809: O << "psp"; return;
case 0x10:
case 0x810: O << "primask"; return;
case 0x11:
case 0x811: O << "basepri"; return;
case 0x12:
case 0x812: O << "basepri_max"; return;
case 0x13:
case 0x813: O << "faultmask"; return;
case 0x14:
case 0x814: O << "control"; return;
}
}

20
test/MC/ARM/thumb2-mclass.s
View File

@ -86,13 +86,13 @@
@ CHECK: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x88]
@ CHECK: msr xpsr_g, r0 @ encoding: [0x80,0xf3,0x03,0x84]
@ CHECK: msr xpsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x03,0x8c]
@ CHECK: msr ipsr, r0 @ encoding: [0x80,0xf3,0x05,0x80]
@ CHECK: msr epsr, r0 @ encoding: [0x80,0xf3,0x06,0x80]
@ CHECK: msr iepsr, r0 @ encoding: [0x80,0xf3,0x07,0x80]
@ CHECK: msr msp, r0 @ encoding: [0x80,0xf3,0x08,0x80]
@ CHECK: msr psp, r0 @ encoding: [0x80,0xf3,0x09,0x80]
@ CHECK: msr primask, r0 @ encoding: [0x80,0xf3,0x10,0x80]
@ CHECK: msr basepri, r0 @ encoding: [0x80,0xf3,0x11,0x80]
@ CHECK: msr basepri_max, r0 @ encoding: [0x80,0xf3,0x12,0x80]
@ CHECK: msr faultmask, r0 @ encoding: [0x80,0xf3,0x13,0x80]
@ CHECK: msr control, r0 @ encoding: [0x80,0xf3,0x14,0x80]
@ CHECK: msr ipsr, r0 @ encoding: [0x80,0xf3,0x05,0x88]
@ CHECK: msr epsr, r0 @ encoding: [0x80,0xf3,0x06,0x88]
@ CHECK: msr iepsr, r0 @ encoding: [0x80,0xf3,0x07,0x88]
@ CHECK: msr msp, r0 @ encoding: [0x80,0xf3,0x08,0x88]
@ CHECK: msr psp, r0 @ encoding: [0x80,0xf3,0x09,0x88]
@ CHECK: msr primask, r0 @ encoding: [0x80,0xf3,0x10,0x88]
@ CHECK: msr basepri, r0 @ encoding: [0x80,0xf3,0x11,0x88]
@ CHECK: msr basepri_max, r0 @ encoding: [0x80,0xf3,0x12,0x88]
@ CHECK: msr faultmask, r0 @ encoding: [0x80,0xf3,0x13,0x88]
@ CHECK: msr control, r0 @ encoding: [0x80,0xf3,0x14,0x88]