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Remove the canCombineSubRegIndices() target hook.
The new coalescer can already do all of this, so there is no need to duplicate the efforts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166813 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
b8b3f6081f
commit
f4a5a613fa
@ -446,18 +446,6 @@ public:
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return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
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}
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/// canCombineSubRegIndices - Given a register class and a list of
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/// subregister indices, return true if it's possible to combine the
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/// subregister indices into one that corresponds to a larger
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/// subregister. Return the new subregister index by reference. Note the
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/// new index may be zero if the given subregisters can be combined to
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/// form the whole register.
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virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
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SmallVectorImpl<unsigned> &SubIndices,
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unsigned &NewSubIdx) const {
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return 0;
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}
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/// getMatchingSuperRegClass - Return a subclass of the specified register
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/// class A so that each register in it has a sub-register of the
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/// specified sub-register index which is in the specified register class B.
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@ -142,8 +142,6 @@ namespace {
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bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);
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void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);
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void CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs, unsigned DstReg);
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/// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part
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/// of the de-ssa process. This replaces sources of REG_SEQUENCE as
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/// sub-register references of the register defined by REG_SEQUENCE.
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@ -1514,127 +1512,6 @@ static MachineInstr *findFirstDef(unsigned Reg, MachineRegisterInfo *MRI) {
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return First;
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}
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/// CoalesceExtSubRegs - If a number of sources of the REG_SEQUENCE are
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/// EXTRACT_SUBREG from the same register and to the same virtual register
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/// with different sub-register indices, attempt to combine the
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/// EXTRACT_SUBREGs and pre-coalesce them. e.g.
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/// %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
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/// %reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
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/// %reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5
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/// Since D subregs 5, 6 can combine to a Q register, we can coalesce
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/// reg1026 to reg1029.
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void
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TwoAddressInstructionPass::CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs,
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unsigned DstReg) {
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SmallSet<unsigned, 4> Seen;
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for (unsigned i = 0, e = Srcs.size(); i != e; ++i) {
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unsigned SrcReg = Srcs[i];
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if (!Seen.insert(SrcReg))
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continue;
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// Check that the instructions are all in the same basic block.
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MachineInstr *SrcDefMI = MRI->getUniqueVRegDef(SrcReg);
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MachineInstr *DstDefMI = MRI->getUniqueVRegDef(DstReg);
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if (!SrcDefMI || !DstDefMI ||
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SrcDefMI->getParent() != DstDefMI->getParent())
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continue;
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// If there are no other uses than copies which feed into
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// the reg_sequence, then we might be able to coalesce them.
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bool CanCoalesce = true;
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SmallVector<unsigned, 4> SrcSubIndices, DstSubIndices;
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for (MachineRegisterInfo::use_nodbg_iterator
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UI = MRI->use_nodbg_begin(SrcReg),
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UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
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MachineInstr *UseMI = &*UI;
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if (!UseMI->isCopy() || UseMI->getOperand(0).getReg() != DstReg) {
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CanCoalesce = false;
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break;
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}
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SrcSubIndices.push_back(UseMI->getOperand(1).getSubReg());
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DstSubIndices.push_back(UseMI->getOperand(0).getSubReg());
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}
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if (!CanCoalesce || SrcSubIndices.size() < 2)
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continue;
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// Check that the source subregisters can be combined.
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std::sort(SrcSubIndices.begin(), SrcSubIndices.end());
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unsigned NewSrcSubIdx = 0;
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if (!TRI->canCombineSubRegIndices(MRI->getRegClass(SrcReg), SrcSubIndices,
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NewSrcSubIdx))
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continue;
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// Check that the destination subregisters can also be combined.
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std::sort(DstSubIndices.begin(), DstSubIndices.end());
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unsigned NewDstSubIdx = 0;
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if (!TRI->canCombineSubRegIndices(MRI->getRegClass(DstReg), DstSubIndices,
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NewDstSubIdx))
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continue;
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// If neither source nor destination can be combined to the full register,
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// just give up. This could be improved if it ever matters.
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if (NewSrcSubIdx != 0 && NewDstSubIdx != 0)
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continue;
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// Now that we know that all the uses are extract_subregs and that those
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// subregs can somehow be combined, scan all the extract_subregs again to
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// make sure the subregs are in the right order and can be composed.
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MachineInstr *SomeMI = 0;
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CanCoalesce = true;
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for (MachineRegisterInfo::use_nodbg_iterator
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UI = MRI->use_nodbg_begin(SrcReg),
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UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
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MachineInstr *UseMI = &*UI;
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assert(UseMI->isCopy());
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unsigned DstSubIdx = UseMI->getOperand(0).getSubReg();
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unsigned SrcSubIdx = UseMI->getOperand(1).getSubReg();
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assert(DstSubIdx != 0 && "missing subreg from RegSequence elimination");
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if ((NewDstSubIdx == 0 &&
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TRI->composeSubRegIndices(NewSrcSubIdx, DstSubIdx) != SrcSubIdx) ||
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(NewSrcSubIdx == 0 &&
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TRI->composeSubRegIndices(NewDstSubIdx, SrcSubIdx) != DstSubIdx)) {
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CanCoalesce = false;
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break;
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}
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// Keep track of one of the uses. Preferably the first one which has a
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// <def,undef> flag.
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if (!SomeMI || UseMI->getOperand(0).isUndef())
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SomeMI = UseMI;
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}
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if (!CanCoalesce)
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continue;
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// Insert a copy to replace the original.
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MachineInstr *CopyMI = BuildMI(*SomeMI->getParent(), SomeMI,
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SomeMI->getDebugLoc(),
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TII->get(TargetOpcode::COPY))
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.addReg(DstReg, RegState::Define |
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getUndefRegState(SomeMI->getOperand(0).isUndef()),
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NewDstSubIdx)
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.addReg(SrcReg, 0, NewSrcSubIdx);
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// Remove all the old extract instructions.
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for (MachineRegisterInfo::use_nodbg_iterator
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UI = MRI->use_nodbg_begin(SrcReg),
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UE = MRI->use_nodbg_end(); UI != UE; ) {
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MachineInstr *UseMI = &*UI;
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++UI;
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if (UseMI == CopyMI)
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continue;
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assert(UseMI->isCopy());
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// Move any kills to the new copy or extract instruction.
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if (UseMI->getOperand(1).isKill()) {
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CopyMI->getOperand(1).setIsKill();
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if (LV)
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// Update live variables
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LV->replaceKillInstruction(SrcReg, UseMI, &*CopyMI);
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}
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UseMI->eraseFromParent();
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}
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}
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}
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static bool HasOtherRegSequenceUses(unsigned Reg, MachineInstr *RegSeq,
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MachineRegisterInfo *MRI) {
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for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
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@ -1770,12 +1647,6 @@ bool TwoAddressInstructionPass::EliminateRegSequences() {
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DEBUG(dbgs() << "Eliminated: " << *MI);
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MI->eraseFromParent();
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}
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// Try coalescing some EXTRACT_SUBREG instructions. This can create
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// INSERT_SUBREG instructions that must have <undef> flags added by
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// LiveIntervalAnalysis, so only run it when LiveVariables is available.
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if (LV)
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CoalesceExtSubRegs(RealSrcs, DstReg);
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}
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RegSequences.clear();
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@ -134,122 +134,6 @@ bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
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return false;
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}
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bool
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ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
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SmallVectorImpl<unsigned> &SubIndices,
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unsigned &NewSubIdx) const {
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unsigned Size = RC->getSize() * 8;
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if (Size < 6)
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return 0;
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NewSubIdx = 0; // Whole register.
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unsigned NumRegs = SubIndices.size();
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if (NumRegs == 8) {
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// 8 D registers -> 1 QQQQ register.
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return (Size == 512 &&
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SubIndices[0] == ARM::dsub_0 &&
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SubIndices[1] == ARM::dsub_1 &&
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SubIndices[2] == ARM::dsub_2 &&
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SubIndices[3] == ARM::dsub_3 &&
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SubIndices[4] == ARM::dsub_4 &&
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SubIndices[5] == ARM::dsub_5 &&
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SubIndices[6] == ARM::dsub_6 &&
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SubIndices[7] == ARM::dsub_7);
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} else if (NumRegs == 4) {
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if (SubIndices[0] == ARM::qsub_0) {
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// 4 Q registers -> 1 QQQQ register.
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return (Size == 512 &&
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SubIndices[1] == ARM::qsub_1 &&
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SubIndices[2] == ARM::qsub_2 &&
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SubIndices[3] == ARM::qsub_3);
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} else if (SubIndices[0] == ARM::dsub_0) {
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// 4 D registers -> 1 QQ register.
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if (Size >= 256 &&
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SubIndices[1] == ARM::dsub_1 &&
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SubIndices[2] == ARM::dsub_2 &&
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SubIndices[3] == ARM::dsub_3) {
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if (Size == 512)
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NewSubIdx = ARM::qqsub_0;
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return true;
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}
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} else if (SubIndices[0] == ARM::dsub_4) {
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// 4 D registers -> 1 QQ register (2nd).
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if (Size == 512 &&
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SubIndices[1] == ARM::dsub_5 &&
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SubIndices[2] == ARM::dsub_6 &&
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SubIndices[3] == ARM::dsub_7) {
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NewSubIdx = ARM::qqsub_1;
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return true;
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}
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} else if (SubIndices[0] == ARM::ssub_0) {
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// 4 S registers -> 1 Q register.
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if (Size >= 128 &&
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SubIndices[1] == ARM::ssub_1 &&
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SubIndices[2] == ARM::ssub_2 &&
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SubIndices[3] == ARM::ssub_3) {
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if (Size >= 256)
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NewSubIdx = ARM::qsub_0;
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return true;
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}
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}
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} else if (NumRegs == 2) {
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if (SubIndices[0] == ARM::qsub_0) {
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// 2 Q registers -> 1 QQ register.
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if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
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if (Size == 512)
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NewSubIdx = ARM::qqsub_0;
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return true;
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}
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} else if (SubIndices[0] == ARM::qsub_2) {
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// 2 Q registers -> 1 QQ register (2nd).
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if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
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NewSubIdx = ARM::qqsub_1;
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return true;
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}
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} else if (SubIndices[0] == ARM::dsub_0) {
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// 2 D registers -> 1 Q register.
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if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
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if (Size >= 256)
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NewSubIdx = ARM::qsub_0;
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return true;
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}
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} else if (SubIndices[0] == ARM::dsub_2) {
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// 2 D registers -> 1 Q register (2nd).
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if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
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NewSubIdx = ARM::qsub_1;
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return true;
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}
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} else if (SubIndices[0] == ARM::dsub_4) {
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// 2 D registers -> 1 Q register (3rd).
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if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
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NewSubIdx = ARM::qsub_2;
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return true;
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}
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} else if (SubIndices[0] == ARM::dsub_6) {
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// 2 D registers -> 1 Q register (3rd).
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if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
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NewSubIdx = ARM::qsub_3;
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return true;
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}
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} else if (SubIndices[0] == ARM::ssub_0) {
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// 2 S registers -> 1 D register.
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if (SubIndices[1] == ARM::ssub_1) {
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if (Size >= 128)
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NewSubIdx = ARM::dsub_0;
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return true;
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}
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} else if (SubIndices[0] == ARM::ssub_2) {
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// 2 S registers -> 1 D register (2nd).
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if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
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NewSubIdx = ARM::dsub_1;
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return true;
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}
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}
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}
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return false;
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}
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const TargetRegisterClass*
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ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
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const {
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@ -99,16 +99,6 @@ public:
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BitVector getReservedRegs(const MachineFunction &MF) const;
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/// canCombineSubRegIndices - Given a register class and a list of
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/// subregister indices, return true if it's possible to combine the
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/// subregister indices into one that corresponds to a larger
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/// subregister. Return the new subregister index by reference. Note the
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/// new index may be zero if the given subregisters can be combined to
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/// form the whole register.
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virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
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SmallVectorImpl<unsigned> &SubIndices,
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unsigned &NewSubIdx) const;
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const TargetRegisterClass*
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getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const;
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const TargetRegisterClass*
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