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Implement the inline asm 'A' constraint. This implements PR825 and
CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29101 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -4135,6 +4135,16 @@ SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
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// X86 Inline Assembly Support
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//===----------------------------------------------------------------------===//
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/// getConstraintType - Given a constraint letter, return the type of
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/// constraint it is for this target.
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X86TargetLowering::ConstraintType
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X86TargetLowering::getConstraintType(char ConstraintLetter) const {
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switch (ConstraintLetter) {
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case 'A': return C_RegisterClass;
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default: return TargetLowering::getConstraintType(ConstraintLetter);
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}
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}
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std::vector<unsigned> X86TargetLowering::
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getRegClassForInlineAsmConstraint(const std::string &Constraint,
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MVT::ValueType VT) const {
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@ -4142,7 +4152,11 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint,
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// FIXME: not handling fp-stack yet!
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// FIXME: not handling MMX registers yet ('y' constraint).
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switch (Constraint[0]) { // GCC X86 Constraint Letters
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default: break; // Unknown constriant letter
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default: break; // Unknown constraint letter
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case 'A': // EAX/EDX
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if (VT == MVT::i32 || VT == MVT::i64)
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return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
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break;
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case 'r': // GENERAL_REGS
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case 'R': // LEGACY_REGS
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if (VT == MVT::i32)
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@ -310,6 +310,8 @@ namespace llvm {
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SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
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ConstraintType getConstraintType(char ConstraintLetter) const;
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std::vector<unsigned>
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getRegClassForInlineAsmConstraint(const std::string &Constraint,
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MVT::ValueType VT) const;
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