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Sink two variables only used in an assert into the assert itself. Should

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fix the release builds with Werror.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212612 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chandler Carruth 2014-07-09 11:13:16 +00:00
parent 4afbd3e941
commit f4fcb0ceab
1 changed files with 3 additions and 3 deletions
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6
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
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@ -2413,7 +2413,6 @@ bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
SDValue DAGTypeLegalizer::WidenVecOp_ZERO_EXTEND(SDNode *N) {
SDLoc DL(N);
EVT VT = N->getValueType(0);
unsigned NumElts = VT.getVectorNumElements();
SDValue InOp = N->getOperand(0);
// If some legalization strategy other than widening is used on the operand,
@ -2422,8 +2421,9 @@ SDValue DAGTypeLegalizer::WidenVecOp_ZERO_EXTEND(SDNode *N) {
if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)
return WidenVecOp_Convert(N);
InOp = GetWidenedVector(InOp);
EVT InVT = InOp.getValueType();
assert(NumElts < InVT.getVectorNumElements() && "Input wasn't widened!");
assert(VT.getVectorNumElements() <
InOp.getValueType().getVectorNumElements() &&
"Input wasn't widened!");
// Use a special DAG node to represent the operation of zero extending the
// low lanes.