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ARM sched model: Add VFP div instruction on Swift

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183271 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Arnold Schwaighofer 2013-06-04 22:16:08 +00:00
parent 858f6f8899
commit f500aa0b24
1 changed files with 16 additions and 0 deletions
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16
lib/Target/ARM/ARMScheduleSwift.td
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@ -2042,6 +2042,22 @@ let SchedModel = SwiftModel in {
(instregex "VST4LN(d|q)(8|16|32)_UPD", (instregex "VST4LN(d|q)(8|16|32)_UPD",
"VST4LN(d|q)(8|16|32)Pseudo_UPD")>; "VST4LN(d|q)(8|16|32)Pseudo_UPD")>;
// 4.2.44 VFP, Divide and Square Root
def SwiftDiv17 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> {
let NumMicroOps = 1;
let Latency = 17;
let ResourceCycles = [1, 15];
}
def SwiftDiv32 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> {
let NumMicroOps = 1;
let Latency = 32;
let ResourceCycles = [1, 30];
}
def : InstRW<[SwiftDiv17], (instregex "VDIVS", "VSQRTS")>;
def : InstRW<[SwiftDiv32], (instregex "VDIVD", "VSQRTD")>;
// Not specified.
def : InstRW<[SwiftWriteP01OneCycle2x], (instregex "ABS")>;
// Preload. // Preload.
def : WriteRes<WritePreLd, [SwiftUnitP2]> { let Latency = 0; def : WriteRes<WritePreLd, [SwiftUnitP2]> { let Latency = 0;
let ResourceCycles = [0]; let ResourceCycles = [0];