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* Fix spelling of `volatile'
* Align comments with tablegen elements git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20103 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -7,6 +7,7 @@
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Alpha register set.
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//
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//===----------------------------------------------------------------------===//
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@ -78,19 +79,18 @@ def F30 : FPR<30, "$f30">; def F31 : FPR<31, "$f31">;
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/// Register classes
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def GPRC : RegisterClass<i64, 64,
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//Volitle
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[R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R27,
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//Non-Volitile
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// Volatile
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[R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
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R23, R24, R25, R27,
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// Non-volatile
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R9, R10, R11, R12, R13, R14, R15, R26, /* R28, */ R29 /* R30, R31*/ ]>;
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//R28 is reserved for the assembler
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// Note: R28 is reserved for the assembler
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//Don't allocate 15, 29, 30, 31
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//Allocation volatiles only for now
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// Don't allocate 15, 29, 30, 31
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// Allocation volatiles only for now
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def FPRC : RegisterClass<f64, 64, [F0, F1,
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F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
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F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
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//Saved:
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// Saved:
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F2, F3, F4, F5, F6, F7, F8, F9
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]>;
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