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Remove the need to cache the subtarget in the X86 TargetRegisterInfo

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classes. Use a Triple instead and simplify a lot of the querying
logic to use lookups on the Triple.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232071 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2015-03-12 17:54:19 +00:00
parent a08ee010be
commit f516a66bdd
3 changed files with 23 additions and 24 deletions
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2
lib/Target/X86/X86InstrInfo.cpp
View File

@ -104,7 +104,7 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
: X86GenInstrInfo(
(STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32),
(STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)),
Subtarget(STI), RI(STI) {
Subtarget(STI), RI(STI.getTargetTriple()) {
static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
{ X86::ADC32ri, X86::ADC32mi, 0 },

38
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -53,26 +53,26 @@ static cl::opt<bool>
EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
cl::desc("Enable use of a base pointer for complex stack frames"));
X86RegisterInfo::X86RegisterInfo(const X86Subtarget &STI)
: X86GenRegisterInfo(
(STI.is64Bit() ? X86::RIP : X86::EIP),
X86_MC::getDwarfRegFlavour(STI.getTargetTriple(), false),
X86_MC::getDwarfRegFlavour(STI.getTargetTriple(), true),
(STI.is64Bit() ? X86::RIP : X86::EIP)),
Subtarget(STI) {
X86RegisterInfo::X86RegisterInfo(const Triple &TT)
: X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
X86_MC::getDwarfRegFlavour(TT, false),
X86_MC::getDwarfRegFlavour(TT, true),
(TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
X86_MC::InitLLVM2SEHRegisterMapping(this);
// Cache some information.
Is64Bit = Subtarget.is64Bit();
IsWin64 = Subtarget.isTargetWin64();
Is64Bit = TT.isArch64Bit();
IsWin64 = Is64Bit && TT.isOSWindows();
// Use a callee-saved register as the base pointer. These registers must
// not conflict with any ABI requirements. For example, in 32-bit mode PIC
// requires GOT in the EBX register before function calls via PLT GOT pointer.
if (Is64Bit) {
SlotSize = 8;
bool Use64BitReg =
Subtarget.isTarget64BitLP64() || Subtarget.isTargetNaCl64();
// This matches the simplified 32-bit pointer code in the data layout
// computation.
// FIXME: Should use the data layout?
bool Use64BitReg = TT.getEnvironment() != Triple::GNUX32;
StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
@ -162,6 +162,7 @@ X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
const TargetRegisterClass *
X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
unsigned Kind) const {
const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
switch (Kind) {
default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
case 0: // Normal GPRs.
@ -173,9 +174,9 @@ X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
return &X86::GR64_NOSPRegClass;
return &X86::GR32_NOSPRegClass;
case 2: // Available for tailcall (not callee-saved GPRs).
if (Subtarget.isTargetWin64())
if (IsWin64)
return &X86::GR64_TCW64RegClass;
else if (Subtarget.is64Bit())
else if (Is64Bit)
return &X86::GR64_TCRegClass;
const Function *F = MF.getFunction();
@ -211,7 +212,7 @@ X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
case X86::GR64RegClassID:
return 12 - FPDiff;
case X86::VR128RegClassID:
return Subtarget.is64Bit() ? 10 : 4;
return Is64Bit ? 10 : 4;
case X86::VR64RegClassID:
return 4;
}
@ -219,6 +220,7 @@ X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
const MCPhysReg *
X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
bool HasAVX = Subtarget.hasAVX();
bool HasAVX512 = Subtarget.hasAVX512();
bool CallsEHReturn = MF->getMMI().callsEHReturn();
@ -280,6 +282,7 @@ X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
const uint32_t *
X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
CallingConv::ID CC) const {
const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
bool HasAVX = Subtarget.hasAVX();
bool HasAVX512 = Subtarget.hasAVX512();
@ -405,7 +408,7 @@ BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
Reserved.set(*AI);
}
}
if (!Is64Bit || !Subtarget.hasAVX512()) {
if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
for (unsigned n = 16; n != 32; ++n) {
for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
Reserved.set(*AI);
@ -568,8 +571,9 @@ unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
return TFI->hasFP(MF) ? FramePtr : StackPtr;
}
unsigned X86RegisterInfo::getPtrSizedFrameRegister(
const MachineFunction &MF) const {
unsigned
X86RegisterInfo::getPtrSizedFrameRegister(const MachineFunction &MF) const {
const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
unsigned FrameReg = getFrameRegister(MF);
if (Subtarget.isTarget64BitILP32())
FrameReg = getX86SubSuperRegister(FrameReg, MVT::i32, false);

7
lib/Target/X86/X86RegisterInfo.h
View File

@ -20,12 +20,7 @@
#include "X86GenRegisterInfo.inc"
namespace llvm {
class X86Subtarget;
class X86RegisterInfo final : public X86GenRegisterInfo {
public:
const X86Subtarget &Subtarget;
private:
/// Is64Bit - Is the target 64-bits.
///
@ -53,7 +48,7 @@ private:
unsigned BasePtr;
public:
X86RegisterInfo(const X86Subtarget &STI);
X86RegisterInfo(const Triple &TT);
// FIXME: This should be tablegen'd like getDwarfRegNum is
int getSEHRegNum(unsigned i) const;