From f51a22e815a7494cbe1aba25d275015a70b5c31d Mon Sep 17 00:00:00 2001
From: Justin Holewinski <jholewinski@nvidia.com>
Date: Fri, 28 Jun 2013 17:58:13 +0000
Subject: [PATCH] [NVPTX] Add (1.0 / sqrt(x)) => rsqrt(x) generation when
 allowable by FP flags

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185178 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/NVPTX/NVPTXInstrInfo.td | 13 ++++++++++++-
 test/CodeGen/NVPTX/rsqrt.ll        | 13 +++++++++++++
 2 files changed, 25 insertions(+), 1 deletion(-)
 create mode 100644 test/CodeGen/NVPTX/rsqrt.ll

diff --git a/lib/Target/NVPTX/NVPTXInstrInfo.td b/lib/Target/NVPTX/NVPTXInstrInfo.td
index 553a6ba703d..b6f75268d63 100644
--- a/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -136,7 +136,8 @@ def hasLDG : Predicate<"Subtarget.hasLDG()">;
 def hasLDU : Predicate<"Subtarget.hasLDU()">;
 def hasGenericLdSt : Predicate<"Subtarget.hasGenericLdSt()">;
 
-def doF32FTZ : Predicate<"UseF32FTZ">;
+def doF32FTZ : Predicate<"UseF32FTZ==1">;
+def doNoF32FTZ : Predicate<"UseF32FTZ==0">;
 
 def doFMAF32      : Predicate<"doFMAF32">;
 def doFMAF32_ftz  : Predicate<"(doFMAF32 && UseF32FTZ)">;
@@ -765,6 +766,16 @@ def FDIV32ri_prec : NVPTXInst<(outs Float32Regs:$dst),
                         (fdiv Float32Regs:$a, fpimm:$b))]>,
                       Requires<[reqPTX20]>;
 
+//
+// F32 rsqrt
+//
+
+def RSQRTF32approx1r : NVPTXInst<(outs Float32Regs:$dst), (ins Float32Regs:$b),
+                       "rsqrt.approx.f32 \t$dst, $b;", []>;
+
+def: Pat<(fdiv FloatConst1, (int_nvvm_sqrt_f Float32Regs:$b)),
+         (RSQRTF32approx1r Float32Regs:$b)>,
+         Requires<[do_DIVF32_FULL, do_SQRTF32_APPROX, doNoF32FTZ]>;
 
 multiclass FPCONTRACT32<string OpcStr, Predicate Pred> {
    def rrr : NVPTXInst<(outs Float32Regs:$dst),
diff --git a/test/CodeGen/NVPTX/rsqrt.ll b/test/CodeGen/NVPTX/rsqrt.ll
new file mode 100644
index 00000000000..d49eebe8a4b
--- /dev/null
+++ b/test/CodeGen/NVPTX/rsqrt.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 -nvptx-prec-divf32=1 -nvptx-prec-sqrtf32=0 | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
+
+declare float @llvm.nvvm.sqrt.f(float)
+
+define float @foo(float %a) {
+; CHECK: rsqrt.approx.f32
+  %val = tail call float @llvm.nvvm.sqrt.f(float %a)
+  %ret = fdiv float 1.0, %val
+  ret float %ret
+}
+  
\ No newline at end of file