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Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114710 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -201,7 +201,6 @@ class Instruction {
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bit isCompare = 0; // Is this instruction a comparison instruction?
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bit isCompare = 0; // Is this instruction a comparison instruction?
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bit isBarrier = 0; // Can control flow fall through this instruction?
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bit isBarrier = 0; // Can control flow fall through this instruction?
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bit isCall = 0; // Is this instruction a call instruction?
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bit isCall = 0; // Is this instruction a call instruction?
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bit isConditionalMove = 0; // Is this instruction a conditional move instr?
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bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
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bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
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bit mayLoad = 0; // Is it possible for this inst to read memory?
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bit mayLoad = 0; // Is it possible for this inst to read memory?
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bit mayStore = 0; // Is it possible for this inst to write memory?
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bit mayStore = 0; // Is it possible for this inst to write memory?
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@ -99,7 +99,6 @@ namespace TID {
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HasOptionalDef,
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HasOptionalDef,
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Return,
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Return,
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Call,
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Call,
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ConditionalMove,
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Barrier,
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Barrier,
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Terminator,
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Terminator,
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Branch,
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Branch,
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@ -353,12 +352,6 @@ public:
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return Flags & (1 << TID::Compare);
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return Flags & (1 << TID::Compare);
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}
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}
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/// isConditionalMove - Return true if this instruction can be considered a
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/// conditional move, like CMOV on X86 or MOVCC on ARM.
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bool isConditionalMove() const {
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return Flags & (1 << TID::ConditionalMove);
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}
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/// isNotDuplicable - Return true if this instruction cannot be safely
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/// isNotDuplicable - Return true if this instruction cannot be safely
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/// duplicated. For example, if the instruction has a unique labels attached
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/// duplicated. For example, if the instruction has a unique labels attached
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/// to it, duplicating it would cause multiple definition errors.
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/// to it, duplicating it would cause multiple definition errors.
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@ -2391,7 +2391,7 @@ def BCCZi64 : PseudoInst<(outs),
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// Conditional moves
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// Conditional moves
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// FIXME: should be able to write a pattern for ARMcmov, but can't use
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// FIXME: should be able to write a pattern for ARMcmov, but can't use
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// a two-value operand where a dag node expects two operands. :(
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// a two-value operand where a dag node expects two operands. :(
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let neverHasSideEffects = 1, isConditionalMove = 1 in {
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let neverHasSideEffects = 1 in {
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def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
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def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
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IIC_iCMOVr, "mov", "\t$dst, $true",
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IIC_iCMOVr, "mov", "\t$dst, $true",
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[/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
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[/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
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@ -2415,7 +2415,7 @@ def MOVCCi : AI1<0b1101, (outs GPR:$dst),
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RegConstraint<"$false = $dst">, UnaryDP {
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RegConstraint<"$false = $dst">, UnaryDP {
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let Inst{25} = 1;
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let Inst{25} = 1;
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}
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}
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} // neverHasSideEffects, isConditionalMove
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} // neverHasSideEffects
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Atomic operations intrinsics
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// Atomic operations intrinsics
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@ -866,7 +866,7 @@ let usesCustomInserter = 1 in // Expanded after instruction selection.
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// 16-bit movcc in IT blocks for Thumb2.
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// 16-bit movcc in IT blocks for Thumb2.
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let neverHasSideEffects = 1, isConditionalMove = 1 in {
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let neverHasSideEffects = 1 in {
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def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
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def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
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"mov", "\t$dst, $rhs", []>,
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"mov", "\t$dst, $rhs", []>,
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T1Special<{1,0,?,?}>;
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T1Special<{1,0,?,?}>;
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@ -874,7 +874,7 @@ def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
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def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
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def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
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"mov", "\t$dst, $rhs", []>,
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"mov", "\t$dst, $rhs", []>,
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T1General<{1,0,0,?,?}>;
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T1General<{1,0,0,?,?}>;
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} // neverHasSideEffects, isConditionalMove
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} // neverHasSideEffects
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// tLEApcrel - Load a pc-relative address into a register without offending the
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// tLEApcrel - Load a pc-relative address into a register without offending the
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// assembler.
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// assembler.
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@ -2169,7 +2169,7 @@ defm t2TEQ : T2I_cmp_irs<0b0100, "teq",
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// Conditional moves
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// Conditional moves
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// FIXME: should be able to write a pattern for ARMcmov, but can't use
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// FIXME: should be able to write a pattern for ARMcmov, but can't use
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// a two-value operand where a dag node expects two operands. :(
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// a two-value operand where a dag node expects two operands. :(
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let neverHasSideEffects = 1, isConditionalMove = 1 in {
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let neverHasSideEffects = 1 in {
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def t2MOVCCr : T2I<(outs rGPR:$dst), (ins rGPR:$false, rGPR:$true), IIC_iCMOVr,
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def t2MOVCCr : T2I<(outs rGPR:$dst), (ins rGPR:$false, rGPR:$true), IIC_iCMOVr,
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"mov", ".w\t$dst, $true",
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"mov", ".w\t$dst, $true",
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[/*(set rGPR:$dst, (ARMcmov rGPR:$false, rGPR:$true, imm:$cc, CCR:$ccr))*/]>,
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[/*(set rGPR:$dst, (ARMcmov rGPR:$false, rGPR:$true, imm:$cc, CCR:$ccr))*/]>,
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@ -2221,7 +2221,7 @@ def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$dst),
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(ins rGPR:$false, rGPR:$true, i32imm:$rhs),
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(ins rGPR:$false, rGPR:$true, i32imm:$rhs),
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IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
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IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>,
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RegConstraint<"$false = $dst">;
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RegConstraint<"$false = $dst">;
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} // neverHasSideEffects, isConditionalMove
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} // neverHasSideEffects
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Atomic operations intrinsics
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// Atomic operations intrinsics
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@ -1366,7 +1366,7 @@ def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
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} // Defs = [EFLAGS]
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} // Defs = [EFLAGS]
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// Conditional moves
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// Conditional moves
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let isConditionalMove = 1, Uses = [EFLAGS], Constraints = "$src1 = $dst" in {
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let Uses = [EFLAGS], Constraints = "$src1 = $dst" in {
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let isCommutable = 1 in {
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let isCommutable = 1 in {
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def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
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def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
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(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
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(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
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@ -1530,7 +1530,7 @@ def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
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"cmovno{q}\t{$src2, $dst|$dst, $src2}",
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"cmovno{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
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[(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
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X86_COND_NO, EFLAGS))]>, TB;
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X86_COND_NO, EFLAGS))]>, TB;
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} // isConditionalMove, Constraints = "$src1 = $dst"
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} // Constraints = "$src1 = $dst"
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// Use sbb to materialize carry flag into a GPR.
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// Use sbb to materialize carry flag into a GPR.
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// FIXME: This are pseudo ops that should be replaced with Pat<> patterns.
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// FIXME: This are pseudo ops that should be replaced with Pat<> patterns.
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@ -1269,7 +1269,7 @@ let Constraints = "$src1 = $dst" in {
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// Conditional moves
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// Conditional moves
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let Uses = [EFLAGS] in {
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let Uses = [EFLAGS] in {
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let isConditionalMove = 1, Predicates = [HasCMov] in {
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let Predicates = [HasCMov] in {
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let isCommutable = 1 in {
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let isCommutable = 1 in {
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def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
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def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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@ -1657,7 +1657,7 @@ def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
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[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
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[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
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X86_COND_NO, EFLAGS))]>,
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X86_COND_NO, EFLAGS))]>,
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TB;
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TB;
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} // isConditionalMove, Predicates = [HasCMov]
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} // Predicates = [HasCMov]
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// X86 doesn't have 8-bit conditional moves. Use a customInserter to
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// X86 doesn't have 8-bit conditional moves. Use a customInserter to
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// emit control flow. An alternative to this is to mark i8 SELECT as Promote,
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// emit control flow. An alternative to this is to mark i8 SELECT as Promote,
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@ -103,7 +103,6 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
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isBranch = R->getValueAsBit("isBranch");
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isBranch = R->getValueAsBit("isBranch");
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isIndirectBranch = R->getValueAsBit("isIndirectBranch");
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isIndirectBranch = R->getValueAsBit("isIndirectBranch");
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isCompare = R->getValueAsBit("isCompare");
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isCompare = R->getValueAsBit("isCompare");
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isConditionalMove = R->getValueAsBit("isConditionalMove");
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isBarrier = R->getValueAsBit("isBarrier");
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isBarrier = R->getValueAsBit("isBarrier");
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isCall = R->getValueAsBit("isCall");
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isCall = R->getValueAsBit("isCall");
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canFoldAsLoad = R->getValueAsBit("canFoldAsLoad");
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canFoldAsLoad = R->getValueAsBit("canFoldAsLoad");
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@ -124,7 +124,6 @@ namespace llvm {
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bool isBranch;
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bool isBranch;
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bool isIndirectBranch;
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bool isIndirectBranch;
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bool isCompare;
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bool isCompare;
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bool isConditionalMove;
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bool isBarrier;
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bool isBarrier;
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bool isCall;
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bool isCall;
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bool canFoldAsLoad;
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bool canFoldAsLoad;
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@ -274,7 +274,6 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
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if (Inst.isBarrier) OS << "|(1<<TID::Barrier)";
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if (Inst.isBarrier) OS << "|(1<<TID::Barrier)";
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if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
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if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
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if (Inst.isCall) OS << "|(1<<TID::Call)";
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if (Inst.isCall) OS << "|(1<<TID::Call)";
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if (Inst.isConditionalMove) OS << "|(1<<TID::ConditionalMove)";
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if (Inst.canFoldAsLoad) OS << "|(1<<TID::FoldableAsLoad)";
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if (Inst.canFoldAsLoad) OS << "|(1<<TID::FoldableAsLoad)";
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if (Inst.mayLoad) OS << "|(1<<TID::MayLoad)";
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if (Inst.mayLoad) OS << "|(1<<TID::MayLoad)";
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if (Inst.mayStore) OS << "|(1<<TID::MayStore)";
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if (Inst.mayStore) OS << "|(1<<TID::MayStore)";
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