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Fix X86FastISel code for comparisons and conditional branches

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to check the result of getRegForValue before using it, and
to check for illegal operand types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55819 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-09-05 01:15:35 +00:00
parent 087c8507e5
commit f52550b50e
1 changed files with 9 additions and 1 deletions
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10
lib/Target/X86/X86FastISel.cpp
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@ -263,10 +263,16 @@ bool X86FastISel::X86SelectCmp(Instruction *I) {
CmpInst *CI = cast<CmpInst>(I); CmpInst *CI = cast<CmpInst>(I);
unsigned Op0Reg = getRegForValue(CI->getOperand(0)); unsigned Op0Reg = getRegForValue(CI->getOperand(0));
if (Op0Reg == 0) return false;
unsigned Op1Reg = getRegForValue(CI->getOperand(1)); unsigned Op1Reg = getRegForValue(CI->getOperand(1));
if (Op1Reg == 0) return false;
MVT VT = TLI.getValueType(I->getOperand(0)->getType());
if (!TLI.isTypeLegal(VT))
return false;
unsigned Opc; unsigned Opc;
switch (TLI.getValueType(I->getOperand(0)->getType()).getSimpleVT()) { switch (VT.getSimpleVT()) {
case MVT::i8: Opc = X86::CMP8rr; break; case MVT::i8: Opc = X86::CMP8rr; break;
case MVT::i16: Opc = X86::CMP16rr; break; case MVT::i16: Opc = X86::CMP16rr; break;
case MVT::i32: Opc = X86::CMP32rr; break; case MVT::i32: Opc = X86::CMP32rr; break;
@ -398,6 +404,7 @@ bool X86FastISel::X86SelectZExt(Instruction *I) {
if (I->getType() == Type::Int8Ty && if (I->getType() == Type::Int8Ty &&
I->getOperand(0)->getType() == Type::Int1Ty) { I->getOperand(0)->getType() == Type::Int1Ty) {
unsigned ResultReg = getRegForValue(I->getOperand(0)); unsigned ResultReg = getRegForValue(I->getOperand(0));
if (ResultReg == 0) return false;
UpdateValueMap(I, ResultReg); UpdateValueMap(I, ResultReg);
return true; return true;
} }
@ -409,6 +416,7 @@ bool X86FastISel::X86SelectBranch(Instruction *I) {
BranchInst *BI = cast<BranchInst>(I); BranchInst *BI = cast<BranchInst>(I);
// Unconditional branches are selected by tablegen-generated code. // Unconditional branches are selected by tablegen-generated code.
unsigned OpReg = getRegForValue(BI->getCondition()); unsigned OpReg = getRegForValue(BI->getCondition());
if (OpReg == 0) return false;
MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)]; MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)]; MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];