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Mips64 arithmetic and logical instructions with one source register and

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immediate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140839 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2011-09-30 02:08:54 +00:00
parent 4ebbf7b8a8
commit f549ab7853
2 changed files with 66 additions and 0 deletions
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30
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -17,6 +17,18 @@
def HasMips64 : Predicate<"Subtarget.hasMips64()">;
def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">;
//===----------------------------------------------------------------------===//
// Mips Operand, Complex Patterns and Transformations Definitions.
//===----------------------------------------------------------------------===//
// Instruction operand types
def simm16_64 : Operand<i64>;
// Unsigned Operand
def uimm16_64 : Operand<i64> {
let PrintMethod = "printUnsignedImm";
}
//===----------------------------------------------------------------------===//
// Instructions specific format
//===----------------------------------------------------------------------===//
@ -30,6 +42,13 @@ class ArithR64<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
let isCommutable = isComm;
}
// Arithmetic 2 register operands
class ArithI64<bits<6> op, string instr_asm, SDNode OpNode,
Operand Od, PatLeaf imm_type> :
FI<op, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, Od:$c),
!strconcat(instr_asm, "\t$dst, $b, $c"),
[(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, imm_type:$c))], IIAlu>;
// Logical
let isCommutable = 1 in
class LogicR64<bits<6> func, string instr_asm, SDNode OpNode>:
@ -37,10 +56,21 @@ class LogicR64<bits<6> func, string instr_asm, SDNode OpNode>:
!strconcat(instr_asm, "\t$dst, $b, $c"),
[(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, CPU64Regs:$c))], IIAlu>;
class LogicI64<bits<6> op, string instr_asm, SDNode OpNode>:
FI<op, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, uimm16_64:$c),
!strconcat(instr_asm, "\t$dst, $b, $c"),
[(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, immZExt16:$c))], IIAlu>;
//===----------------------------------------------------------------------===//
// Instruction definition
//===----------------------------------------------------------------------===//
/// Arithmetic Instructions (ALU Immediate)
def DADDiu : ArithI64<0x19, "daddiu", add, simm16_64, immSExt16>;
def DANDi : LogicI64<0x0c, "andi", and>;
def DORi : LogicI64<0x0d, "ori", or>;
def DXORi : LogicI64<0x0e, "xori", xor>;
/// Arithmetic Instructions (3-Operand, R-Type)
def DADDu : ArithR64<0x00, 0x2d, "daddu", add, IIAlu, 1>;
def DSUBu : ArithR64<0x00, 0x2f, "dsubu", sub, IIAlu, 1>;

36
test/CodeGen/Mips/mips64instrs.ll
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@ -34,3 +34,39 @@ entry:
%xor = xor i64 %a1, %a0
ret i64 %xor
}
define i64 @f7(i64 %a0) nounwind readnone {
entry:
; CHECK: daddiu
%add = add nsw i64 %a0, 20
ret i64 %add
}
define i64 @f8(i64 %a0) nounwind readnone {
entry:
; CHECK: daddiu
%sub = add nsw i64 %a0, -20
ret i64 %sub
}
define i64 @f9(i64 %a0) nounwind readnone {
entry:
; CHECK: andi
%and = and i64 %a0, 20
ret i64 %and
}
define i64 @f10(i64 %a0) nounwind readnone {
entry:
; CHECK: ori
%or = or i64 %a0, 20
ret i64 %or
}
define i64 @f11(i64 %a0) nounwind readnone {
entry:
; CHECK: xori
%xor = xor i64 %a0, 20
ret i64 %xor
}