diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index 23238ad9e05..e6f18ea43f8 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -340,12 +340,20 @@ public: return (LegalizeAction)((OpActions[Op] >> (2*VT.getSimpleVT())) & 3); } + /// isOperationLegalOrCustom - Return true if the specified operation is + /// legal on this target or can be made legal with custom lowering. This + /// is used to help guide high-level lowering decisions. + bool isOperationLegalOrCustom(unsigned Op, MVT VT) const { + return (VT == MVT::Other || isTypeLegal(VT)) && + (getOperationAction(Op, VT) == Legal || + getOperationAction(Op, VT) == Custom); + } + /// isOperationLegal - Return true if the specified operation is legal on this /// target. bool isOperationLegal(unsigned Op, MVT VT) const { return (VT == MVT::Other || isTypeLegal(VT)) && - (getOperationAction(Op, VT) == Legal || - getOperationAction(Op, VT) == Custom); + getOperationAction(Op, VT) == Legal; } /// getLoadExtAction - Return how this load with extension should be treated: diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index d4df880d0be..48e556b2362 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -2054,8 +2054,8 @@ SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) { if (!TLI.isTypeLegal(VT)) return 0; // The target must have at least one rotate flavor. - bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); - bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); + bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); + bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); if (!HasROTL && !HasROTR) return 0; // Match "(X shl/srl V1) & V2" where V2 may not be present. @@ -2541,8 +2541,8 @@ SDValue DAGCombiner::visitSRA(SDNode *N) { // on that type, and the the truncate to that type is both legal and free, // perform the transform. if (ShiftAmt && - TLI.isOperationLegal(ISD::SIGN_EXTEND, TruncVT) && - TLI.isOperationLegal(ISD::TRUNCATE, VT) && + TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && + TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && TLI.isTruncateFree(VT, TruncVT)) { SDValue Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy()); @@ -2795,7 +2795,7 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) { // Check against MVT::Other for SELECT_CC, which is a workaround for targets // having to say they don't support SELECT_CC on every type the DAG knows // about, since there is no way to mark an opcode illegal at all value types - if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) + if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), N1, N2, N0.getOperand(2)); else @@ -4032,8 +4032,8 @@ SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { // If the input is a legal type, and SINT_TO_FP is not legal on this target, // but UINT_TO_FP is legal on this target, try to convert. - if (!TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT) && - TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT)) { + if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && + TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { // If the sign bit is known to be zero, we can change this to UINT_TO_FP. if (DAG.SignBitIsZero(N0)) return DAG.getNode(ISD::UINT_TO_FP, VT, N0); @@ -4055,8 +4055,8 @@ SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { // If the input is a legal type, and UINT_TO_FP is not legal on this target, // but SINT_TO_FP is legal on this target, try to convert. - if (!TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT) && - TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT)) { + if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && + TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { // If the sign bit is known to be zero, we can change this to SINT_TO_FP. if (DAG.SignBitIsZero(N0)) return DAG.getNode(ISD::SINT_TO_FP, VT, N0); @@ -4252,7 +4252,7 @@ SDValue DAGCombiner::visitBRCOND(SDNode *N) { // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal // on the target. if (N1.getOpcode() == ISD::SETCC && - TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { + TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), N1.getOperand(0), N1.getOperand(1), N2); } @@ -4726,7 +4726,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) { getABITypeAlignment(SVT.getTypeForMVT()); if (Align <= OrigAlign && ((!LegalOperations && !ST->isVolatile()) || - TLI.isOperationLegal(ISD::STORE, SVT))) + TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); } @@ -4747,7 +4747,8 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) { break; case MVT::f32: if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && - !ST->isVolatile()) || TLI.isOperationLegal(ISD::STORE, MVT::i32)) { + !ST->isVolatile()) || + TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). bitcastToAPInt().getZExtValue(), MVT::i32); return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), @@ -4757,14 +4758,15 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) { break; case MVT::f64: if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && - !ST->isVolatile()) || TLI.isOperationLegal(ISD::STORE, MVT::i64)) { + !ST->isVolatile()) || + TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). getZExtValue(), MVT::i64); return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), ST->getSrcValueOffset(), ST->isVolatile(), ST->getAlignment()); } else if (!ST->isVolatile() && - TLI.isOperationLegal(ISD::STORE, MVT::i32)) { + TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { // Many FP stores are not made apparent until after legalize, e.g. for // argument passing. Since this is so common, custom legalize the // 64-bit integer store into two 32-bit stores. @@ -4967,7 +4969,7 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { // original load. unsigned NewAlign = TLI.getTargetData()-> getABITypeAlignment(LVT.getTypeForMVT()); - if (NewAlign > Align || !TLI.isOperationLegal(ISD::LOAD, LVT)) + if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) return SDValue(); Align = NewAlign; } diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 2183431e1aa..5b8d18ce214 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -1263,8 +1263,9 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { default: assert(0 && "This action is not supported yet!"); case TargetLowering::Expand: { DwarfWriter *DW = DAG.getDwarfWriter(); - bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); - bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other); + bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC, + MVT::Other); + bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other); const DbgStopPointSDNode *DSP = cast(Node); GlobalVariable *CU_GV = cast(DSP->getCompileUnit()); @@ -3065,7 +3066,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { "Fell off of the edge of the floating point world"); // If the target supports SETCC of this type, use it. - if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) + if (TLI.isOperationLegalOrCustom(ISD::SETCC, NewInTy)) break; } if (NewInTy.isInteger()) @@ -3228,10 +3229,10 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { // and unsigned forms. If the target supports both SMUL_LOHI and // UMUL_LOHI, form a preference by checking which forms of plain // MULH it supports. - bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT); - bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT); - bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT); - bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT); + bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); + bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); + bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); + bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); unsigned OpToUse = 0; if (HasSMUL_LOHI && !HasMULHS) { OpToUse = ISD::SMUL_LOHI; @@ -3248,25 +3249,25 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { } } if (Node->getOpcode() == ISD::MULHS && - TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) { + TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) { Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), 1); break; } if (Node->getOpcode() == ISD::MULHU && - TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) { + TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) { Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), 1); break; } if (Node->getOpcode() == ISD::SDIV && - TLI.isOperationLegal(ISD::SDIVREM, VT)) { + TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) { Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 0); break; } if (Node->getOpcode() == ISD::UDIV && - TLI.isOperationLegal(ISD::UDIVREM, VT)) { + TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) { Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 0); break; @@ -3510,12 +3511,12 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { // See if remainder can be lowered using two-result operations. SDVTList VTs = DAG.getVTList(VT, VT); if (Node->getOpcode() == ISD::SREM && - TLI.isOperationLegal(ISD::SDIVREM, VT)) { + TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) { Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1); break; } if (Node->getOpcode() == ISD::UREM && - TLI.isOperationLegal(ISD::UDIVREM, VT)) { + TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) { Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1); break; } @@ -4639,8 +4640,8 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not // legal, such as PowerPC. if (Node->getOpcode() == ISD::FP_TO_UINT && - !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && - (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || + !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) && + (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT) || TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); } else { @@ -5549,7 +5550,8 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { &MaskVec[0], MaskVec.size()); // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it. - if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && + if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR, + Node->getValueType(0)) && isShuffleLegal(Node->getValueType(0), ShuffleMask)) { Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1); Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2); @@ -6330,8 +6332,8 @@ SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) { SDValue Tmp3 = DAG.getNode(ISD::AND, VT, DAG.getNOT(Op, VT), DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. - if (!TLI.isOperationLegal(ISD::CTPOP, VT) && - TLI.isOperationLegal(ISD::CTLZ, VT)) + if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && + TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) return DAG.getNode(ISD::SUB, VT, DAG.getConstant(VT.getSizeInBits(), VT), DAG.getNode(ISD::CTLZ, VT, Tmp3)); @@ -6821,8 +6823,9 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){ // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit // this X << 1 as X+X. if (ConstantSDNode *ShAmt = dyn_cast(ShiftAmt)) { - if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && - TLI.isOperationLegal(ISD::ADDE, NVT)) { + if (ShAmt->getAPIntValue() == 1 && + TLI.isOperationLegalOrCustom(ISD::ADDC, NVT) && + TLI.isOperationLegalOrCustom(ISD::ADDE, NVT)) { SDValue LoOps[2], HiOps[3]; ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); @@ -6944,7 +6947,7 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){ bool hasCarry = false; for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) { MVT AVT = MVT::getIntegerVT(BitSize); - if (TLI.isOperationLegal(OpV, AVT)) { + if (TLI.isOperationLegalOrCustom(OpV, AVT)) { hasCarry = true; break; } @@ -7041,10 +7044,10 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){ } } - bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); - bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); - bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); - bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); + bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT); + bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT); + bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT); + bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT); if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { SDValue LL, LH, RL, RH; ExpandOp(Node->getOperand(0), LL, LH); diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index b5b249a2254..f3897fad1d0 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -345,8 +345,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not // legal, such as PowerPC. if (N->getOpcode() == ISD::FP_TO_UINT && - !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && - TLI.isOperationLegal(ISD::FP_TO_SINT, NVT)) + !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) && + TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) NewOpc = ISD::FP_TO_SINT; SDValue Res = DAG.getNode(NewOpc, NVT, N->getOperand(0)); @@ -1008,7 +1008,8 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, Lo = DAG.getConstant(0, NVT); Hi = InL; } else if (Amt == 1 && - TLI.isOperationLegal(ISD::ADDC, TLI.getTypeToExpandTo(NVT))) { + TLI.isOperationLegalOrCustom(ISD::ADDC, + TLI.getTypeToExpandTo(NVT))) { // Emit this X << 1 as X+X. SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); SDValue LoOps[2] = { InL, InL }; @@ -1166,8 +1167,9 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, // a carry of type MVT::Flag, but there doesn't seem to be any way to // generate a value of this type in the expanded code sequence. bool hasCarry = - TLI.isOperationLegal(N->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC, - TLI.getTypeToExpandTo(NVT)); + TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ? + ISD::ADDC : ISD::SUBC, + TLI.getTypeToExpandTo(NVT)); if (hasCarry) { SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); @@ -1513,10 +1515,10 @@ void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, MVT VT = N->getValueType(0); MVT NVT = TLI.getTypeToTransformTo(VT); - bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); - bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); - bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); - bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); + bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT); + bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT); + bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT); + bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT); if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { SDValue LL, LH, RL, RH; GetExpandedInteger(N->getOperand(0), LL, LH); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp index b543b9e63fd..a0154cb0a0d 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp @@ -1588,8 +1588,8 @@ bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, static inline bool areJTsAllowed(const TargetLowering &TLI) { return !DisableJumpTables && - (TLI.isOperationLegal(ISD::BR_JT, MVT::Other) || - TLI.isOperationLegal(ISD::BRIND, MVT::Other)); + (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || + TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); } static APInt ComputeRange(const APInt &First, const APInt &Last) { diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index cd5df4ff091..7245244684d 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -2365,10 +2365,10 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, // Multiply the numerator (operand 0) by the magic value // FIXME: We should support doing a MUL in a wider type SDValue Q; - if (isOperationLegal(ISD::MULHS, VT)) + if (isOperationLegalOrCustom(ISD::MULHS, VT)) Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), DAG.getConstant(magics.m, VT)); - else if (isOperationLegal(ISD::SMUL_LOHI, VT)) + else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT), N->getOperand(0), DAG.getConstant(magics.m, VT)).getNode(), 1); @@ -2423,10 +2423,10 @@ SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, // Multiply the numerator (operand 0) by the magic value // FIXME: We should support doing a MUL in a wider type SDValue Q; - if (isOperationLegal(ISD::MULHU, VT)) + if (isOperationLegalOrCustom(ISD::MULHU, VT)) Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), DAG.getConstant(magics.m, VT)); - else if (isOperationLegal(ISD::UMUL_LOHI, VT)) + else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT), N->getOperand(0), DAG.getConstant(magics.m, VT)).getNode(), 1);