mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-26 07:29:55 +00:00
Finish converting the rest of the NEON VLD instructions to use pseudo-
instructions prior to regalloc. Since it's getting a little close to the 2.8 branch deadline, I'll have to leave the rest of the instructions handled by the NEONPreAllocPass for now, but I didn't want to leave half of the VLD instructions converted and the other half not. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112983 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
parent
2465dcf4c8
commit
f572191fe4
@ -105,16 +105,17 @@ void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI,
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D2 = TRI->getSubReg(DstReg, ARM::dsub_5);
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D3 = TRI->getSubReg(DstReg, ARM::dsub_7);
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}
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MIB.addReg(D0).addReg(D1);
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MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
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.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
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if (NumRegs > 2)
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MIB.addReg(D2);
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MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
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if (NumRegs > 3)
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MIB.addReg(D3);
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MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
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if (hasWriteBack) {
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bool WBIsDead = MI.getOperand(OpIdx).isDead();
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unsigned WBReg = MI.getOperand(OpIdx++).getReg();
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MIB.addReg(WBReg, getDefRegState(true) | getDeadRegState(WBIsDead));
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MIB.addReg(WBReg, RegState::Define | getDeadRegState(WBIsDead));
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}
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// Copy the addrmode6 operands.
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bool AddrIsKill = MI.getOperand(OpIdx).isKill();
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@ -128,9 +129,12 @@ void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI,
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MIB = AddDefaultPred(MIB);
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TransferImpOps(MI, MIB, MIB);
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// Add an implicit def for the super-reg.
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MIB.addReg(DstReg, (getDefRegState(true) | getDeadRegState(DstIsDead) |
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getImplRegState(true)));
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// For an instruction writing the odd subregs, add an implicit use of the
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// super-register because the even subregs were loaded separately.
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if (RegSpc == OddDblSpc)
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MIB.addReg(DstReg, RegState::Implicit);
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// Add an implicit def for the super-register.
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MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
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MI.eraseFromParent();
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}
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@ -147,7 +151,7 @@ void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI,
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if (hasWriteBack) {
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bool DstIsDead = MI.getOperand(OpIdx).isDead();
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unsigned DstReg = MI.getOperand(OpIdx++).getReg();
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MIB.addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead));
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MIB.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead));
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}
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// Copy the addrmode6 operands.
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bool AddrIsKill = MI.getOperand(OpIdx).isKill();
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@ -336,15 +340,63 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
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case ARM::VLD2q32Pseudo_UPD:
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ExpandVLD(MBBI, ARM::VLD2q32, true, SingleSpc, 4); break;
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case ARM::VLD3d8Pseudo:
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ExpandVLD(MBBI, ARM::VLD3d8, false, SingleSpc, 3); break;
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case ARM::VLD3d16Pseudo:
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ExpandVLD(MBBI, ARM::VLD3d16, false, SingleSpc, 3); break;
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case ARM::VLD3d32Pseudo:
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ExpandVLD(MBBI, ARM::VLD3d32, false, SingleSpc, 3); break;
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case ARM::VLD1d64TPseudo:
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ExpandVLD(MBBI, ARM::VLD1d64T, false, SingleSpc, 3); break;
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case ARM::VLD3d8Pseudo_UPD:
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ExpandVLD(MBBI, ARM::VLD3d8_UPD, true, SingleSpc, 3); break;
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case ARM::VLD3d16Pseudo_UPD:
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ExpandVLD(MBBI, ARM::VLD3d16_UPD, true, SingleSpc, 3); break;
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case ARM::VLD3d32Pseudo_UPD:
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ExpandVLD(MBBI, ARM::VLD3d32_UPD, true, SingleSpc, 3); break;
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case ARM::VLD1d64TPseudo_UPD:
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ExpandVLD(MBBI, ARM::VLD1d64T, true, SingleSpc, 3); break;
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ExpandVLD(MBBI, ARM::VLD1d64T_UPD, true, SingleSpc, 3); break;
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case ARM::VLD3q8Pseudo_UPD:
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ExpandVLD(MBBI, ARM::VLD3q8_UPD, true, EvenDblSpc, 3); break;
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case ARM::VLD3q16Pseudo_UPD:
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ExpandVLD(MBBI, ARM::VLD3q16_UPD, true, EvenDblSpc, 3); break;
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case ARM::VLD3q32Pseudo_UPD:
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ExpandVLD(MBBI, ARM::VLD3q32_UPD, true, EvenDblSpc, 3); break;
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case ARM::VLD3q8oddPseudo_UPD:
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ExpandVLD(MBBI, ARM::VLD3q8_UPD, true, OddDblSpc, 3); break;
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case ARM::VLD3q16oddPseudo_UPD:
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ExpandVLD(MBBI, ARM::VLD3q16_UPD, true, OddDblSpc, 3); break;
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case ARM::VLD3q32oddPseudo_UPD:
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ExpandVLD(MBBI, ARM::VLD3q32_UPD, true, OddDblSpc, 3); break;
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case ARM::VLD4d8Pseudo:
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ExpandVLD(MBBI, ARM::VLD4d8, false, SingleSpc, 4); break;
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case ARM::VLD4d16Pseudo:
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ExpandVLD(MBBI, ARM::VLD4d16, false, SingleSpc, 4); break;
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case ARM::VLD4d32Pseudo:
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ExpandVLD(MBBI, ARM::VLD4d32, false, SingleSpc, 4); break;
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case ARM::VLD1d64QPseudo:
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ExpandVLD(MBBI, ARM::VLD1d64Q, false, SingleSpc, 4); break;
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case ARM::VLD4d8Pseudo_UPD:
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ExpandVLD(MBBI, ARM::VLD4d8_UPD, true, SingleSpc, 4); break;
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case ARM::VLD4d16Pseudo_UPD:
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ExpandVLD(MBBI, ARM::VLD4d16_UPD, true, SingleSpc, 4); break;
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case ARM::VLD4d32Pseudo_UPD:
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ExpandVLD(MBBI, ARM::VLD4d32_UPD, true, SingleSpc, 4); break;
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case ARM::VLD1d64QPseudo_UPD:
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ExpandVLD(MBBI, ARM::VLD1d64Q, true, SingleSpc, 4); break;
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ExpandVLD(MBBI, ARM::VLD1d64Q_UPD, true, SingleSpc, 4); break;
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case ARM::VLD4q8Pseudo_UPD:
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ExpandVLD(MBBI, ARM::VLD4q8_UPD, true, EvenDblSpc, 4); break;
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case ARM::VLD4q16Pseudo_UPD:
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ExpandVLD(MBBI, ARM::VLD4q16_UPD, true, EvenDblSpc, 4); break;
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case ARM::VLD4q32Pseudo_UPD:
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ExpandVLD(MBBI, ARM::VLD4q32_UPD, true, EvenDblSpc, 4); break;
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case ARM::VLD4q8oddPseudo_UPD:
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ExpandVLD(MBBI, ARM::VLD4q8_UPD, true, OddDblSpc, 4); break;
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case ARM::VLD4q16oddPseudo_UPD:
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ExpandVLD(MBBI, ARM::VLD4q16_UPD, true, OddDblSpc, 4); break;
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case ARM::VLD4q32oddPseudo_UPD:
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ExpandVLD(MBBI, ARM::VLD4q32_UPD, true, OddDblSpc, 4); break;
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case ARM::VST1q8Pseudo:
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ExpandVST(MBBI, ARM::VST1q8, false, SingleSpc, 2); break;
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@ -1111,120 +1111,79 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
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break;
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}
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EVT ResTy;
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if (NumVecs == 1)
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ResTy = VT;
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else {
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unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
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if (!is64BitVector)
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ResTyElts *= 2;
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ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
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}
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SDValue Pred = getAL(CurDAG);
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SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
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SDValue SuperReg;
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if (is64BitVector) {
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unsigned Opc = DOpcodes[OpcodeIndex];
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const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
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SDNode *VLd;
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if (NumVecs <= 2) {
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EVT ResTy;
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if (NumVecs == 1)
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ResTy = VT;
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else
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ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, NumVecs);
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VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5);
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} else {
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std::vector<EVT> ResTys(NumVecs, VT);
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ResTys.push_back(MVT::Other);
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VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5);
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}
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SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5);
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if (NumVecs == 1)
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return VLd;
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SDValue SuperReg;
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if (NumVecs <= 2)
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SuperReg = SDValue(VLd, 0);
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else {
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SDValue V0 = SDValue(VLd, 0);
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SDValue V1 = SDValue(VLd, 1);
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// Form a REG_SEQUENCE to force register allocation.
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SDValue V2 = SDValue(VLd, 2);
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// If it's a vld3, form a quad D-register but discard the last part.
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SDValue V3 = (NumVecs == 3)
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? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
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: SDValue(VLd, 3);
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SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
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}
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SuperReg = SDValue(VLd, 0);
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assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
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for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
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SDValue D = CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec,
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dl, VT, SuperReg);
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ReplaceUses(SDValue(N, Vec), D);
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}
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ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, NumVecs <= 2 ? 1 : NumVecs));
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ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
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return NULL;
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}
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EVT RegVT = GetNEONSubregVT(VT);
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if (NumVecs <= 2) {
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// Quad registers are directly supported for VLD1 and VLD2,
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// loading pairs of D regs.
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unsigned Opc = QOpcodes0[OpcodeIndex];
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const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
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EVT ResTy;
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if (NumVecs == 1)
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ResTy = VT;
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else
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ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, 2 * NumVecs);
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SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5);
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// Combine the even and odd subregs to produce the result.
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if (NumVecs == 1)
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return VLd;
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SDValue QQ = SDValue(VLd, 0);
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SuperReg = SDValue(VLd, 0);
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Chain = SDValue(VLd, 1);
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SDValue Q0 = CurDAG->getTargetExtractSubreg(ARM::qsub_0, dl, VT, QQ);
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SDValue Q1 = CurDAG->getTargetExtractSubreg(ARM::qsub_1, dl, VT, QQ);
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ReplaceUses(SDValue(N, 0), Q0);
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ReplaceUses(SDValue(N, 1), Q1);
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} else {
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// Otherwise, quad registers are loaded with two separate instructions,
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// where one loads the even registers and the other loads the odd registers.
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std::vector<EVT> ResTys(NumVecs, RegVT);
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ResTys.push_back(MemAddr.getValueType());
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ResTys.push_back(MVT::Other);
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EVT AddrTy = MemAddr.getValueType();
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// Load the even subregs.
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unsigned Opc = QOpcodes0[OpcodeIndex];
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const SDValue OpsA[] = { MemAddr, Align, Reg0, Pred, Reg0, Chain };
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SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 6);
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Chain = SDValue(VLdA, NumVecs+1);
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SDValue ImplDef =
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SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
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const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
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SDNode *VLdA =
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CurDAG->getMachineNode(Opc, dl, ResTy, AddrTy, MVT::Other, OpsA, 7);
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Chain = SDValue(VLdA, 2);
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// Load the odd subregs.
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Opc = QOpcodes1[OpcodeIndex];
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const SDValue OpsB[] = { SDValue(VLdA, NumVecs),
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Align, Reg0, Pred, Reg0, Chain };
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SDNode *VLdB = CurDAG->getMachineNode(Opc, dl, ResTys, OpsB, 6);
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Chain = SDValue(VLdB, NumVecs+1);
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const SDValue OpsB[] = { SDValue(VLdA, 1), Align, Reg0, SDValue(VLdA, 0),
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Pred, Reg0, Chain };
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SDNode *VLdB =
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CurDAG->getMachineNode(Opc, dl, ResTy, AddrTy, MVT::Other, OpsB, 7);
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SuperReg = SDValue(VLdB, 0);
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Chain = SDValue(VLdB, 2);
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}
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SDValue V0 = SDValue(VLdA, 0);
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SDValue V1 = SDValue(VLdB, 0);
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SDValue V2 = SDValue(VLdA, 1);
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SDValue V3 = SDValue(VLdB, 1);
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SDValue V4 = SDValue(VLdA, 2);
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SDValue V5 = SDValue(VLdB, 2);
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SDValue V6 = (NumVecs == 3)
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? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,RegVT), 0)
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: SDValue(VLdA, 3);
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SDValue V7 = (NumVecs == 3)
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? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,RegVT), 0)
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: SDValue(VLdB, 3);
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SDValue RegSeq = SDValue(OctoDRegs(MVT::v8i64, V0, V1, V2, V3,
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V4, V5, V6, V7), 0);
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// Extract out the 3 / 4 Q registers.
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assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
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for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
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SDValue Q = CurDAG->getTargetExtractSubreg(ARM::qsub_0+Vec,
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dl, VT, RegSeq);
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ReplaceUses(SDValue(N, Vec), Q);
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}
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// Extract out the Q registers.
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assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
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for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
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SDValue Q = CurDAG->getTargetExtractSubreg(ARM::qsub_0+Vec,
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dl, VT, SuperReg);
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ReplaceUses(SDValue(N, Vec), Q);
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}
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ReplaceUses(SDValue(N, NumVecs), Chain);
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return NULL;
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@ -2166,26 +2125,26 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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}
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case Intrinsic::arm_neon_vld3: {
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unsigned DOpcodes[] = { ARM::VLD3d8, ARM::VLD3d16,
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ARM::VLD3d32, ARM::VLD1d64T };
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unsigned QOpcodes0[] = { ARM::VLD3q8_UPD,
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ARM::VLD3q16_UPD,
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ARM::VLD3q32_UPD };
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unsigned QOpcodes1[] = { ARM::VLD3q8odd_UPD,
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ARM::VLD3q16odd_UPD,
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ARM::VLD3q32odd_UPD };
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unsigned DOpcodes[] = { ARM::VLD3d8Pseudo, ARM::VLD3d16Pseudo,
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ARM::VLD3d32Pseudo, ARM::VLD1d64TPseudo };
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unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
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ARM::VLD3q16Pseudo_UPD,
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ARM::VLD3q32Pseudo_UPD };
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unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
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ARM::VLD3q16oddPseudo_UPD,
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ARM::VLD3q32oddPseudo_UPD };
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return SelectVLD(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
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}
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case Intrinsic::arm_neon_vld4: {
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unsigned DOpcodes[] = { ARM::VLD4d8, ARM::VLD4d16,
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ARM::VLD4d32, ARM::VLD1d64Q };
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unsigned QOpcodes0[] = { ARM::VLD4q8_UPD,
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ARM::VLD4q16_UPD,
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ARM::VLD4q32_UPD };
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unsigned QOpcodes1[] = { ARM::VLD4q8odd_UPD,
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ARM::VLD4q16odd_UPD,
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ARM::VLD4q32odd_UPD };
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unsigned DOpcodes[] = { ARM::VLD4d8Pseudo, ARM::VLD4d16Pseudo,
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ARM::VLD4d32Pseudo, ARM::VLD1d64QPseudo };
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unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
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ARM::VLD4q16Pseudo_UPD,
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ARM::VLD4q32Pseudo_UPD };
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unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
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ARM::VLD4q16oddPseudo_UPD,
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ARM::VLD4q32oddPseudo_UPD };
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return SelectVLD(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
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}
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@ -181,6 +181,10 @@ class VLDQQWBPseudo
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: PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset), IIC_VST,
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"$addr.addr = $wb">;
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class VLDQQQQWBPseudo
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: PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), IIC_VST,
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"$addr.addr = $wb, $src = $dst">;
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// VLD1 : Vector Load (multiple single elements)
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class VLD1D<bits<4> op7_4, string Dt>
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@ -356,6 +360,10 @@ def VLD3d8 : VLD3D<0b0100, 0b0000, "8">;
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def VLD3d16 : VLD3D<0b0100, 0b0100, "16">;
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def VLD3d32 : VLD3D<0b0100, 0b1000, "32">;
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def VLD3d8Pseudo : VLDQQPseudo;
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def VLD3d16Pseudo : VLDQQPseudo;
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def VLD3d32Pseudo : VLDQQPseudo;
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// ...with address register writeback:
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class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
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: NLdSt<0, 0b10, op11_8, op7_4,
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@ -368,6 +376,10 @@ def VLD3d8_UPD : VLD3DWB<0b0100, 0b0000, "8">;
|
||||
def VLD3d16_UPD : VLD3DWB<0b0100, 0b0100, "16">;
|
||||
def VLD3d32_UPD : VLD3DWB<0b0100, 0b1000, "32">;
|
||||
|
||||
def VLD3d8Pseudo_UPD : VLDQQWBPseudo;
|
||||
def VLD3d16Pseudo_UPD : VLDQQWBPseudo;
|
||||
def VLD3d32Pseudo_UPD : VLDQQWBPseudo;
|
||||
|
||||
// ...with double-spaced registers (non-updating versions for disassembly only):
|
||||
def VLD3q8 : VLD3D<0b0101, 0b0000, "8">;
|
||||
def VLD3q16 : VLD3D<0b0101, 0b0100, "16">;
|
||||
@ -376,10 +388,14 @@ def VLD3q8_UPD : VLD3DWB<0b0101, 0b0000, "8">;
|
||||
def VLD3q16_UPD : VLD3DWB<0b0101, 0b0100, "16">;
|
||||
def VLD3q32_UPD : VLD3DWB<0b0101, 0b1000, "32">;
|
||||
|
||||
def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo;
|
||||
def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo;
|
||||
def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo;
|
||||
|
||||
// ...alternate versions to be allocated odd register numbers:
|
||||
def VLD3q8odd_UPD : VLD3DWB<0b0101, 0b0000, "8">;
|
||||
def VLD3q16odd_UPD : VLD3DWB<0b0101, 0b0100, "16">;
|
||||
def VLD3q32odd_UPD : VLD3DWB<0b0101, 0b1000, "32">;
|
||||
def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo;
|
||||
def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo;
|
||||
def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo;
|
||||
|
||||
// VLD4 : Vector Load (multiple 4-element structures)
|
||||
class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
|
||||
@ -392,6 +408,10 @@ def VLD4d8 : VLD4D<0b0000, 0b0000, "8">;
|
||||
def VLD4d16 : VLD4D<0b0000, 0b0100, "16">;
|
||||
def VLD4d32 : VLD4D<0b0000, 0b1000, "32">;
|
||||
|
||||
def VLD4d8Pseudo : VLDQQPseudo;
|
||||
def VLD4d16Pseudo : VLDQQPseudo;
|
||||
def VLD4d32Pseudo : VLDQQPseudo;
|
||||
|
||||
// ...with address register writeback:
|
||||
class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
|
||||
: NLdSt<0, 0b10, op11_8, op7_4,
|
||||
@ -404,6 +424,10 @@ def VLD4d8_UPD : VLD4DWB<0b0000, 0b0000, "8">;
|
||||
def VLD4d16_UPD : VLD4DWB<0b0000, 0b0100, "16">;
|
||||
def VLD4d32_UPD : VLD4DWB<0b0000, 0b1000, "32">;
|
||||
|
||||
def VLD4d8Pseudo_UPD : VLDQQWBPseudo;
|
||||
def VLD4d16Pseudo_UPD : VLDQQWBPseudo;
|
||||
def VLD4d32Pseudo_UPD : VLDQQWBPseudo;
|
||||
|
||||
// ...with double-spaced registers (non-updating versions for disassembly only):
|
||||
def VLD4q8 : VLD4D<0b0001, 0b0000, "8">;
|
||||
def VLD4q16 : VLD4D<0b0001, 0b0100, "16">;
|
||||
@ -412,10 +436,14 @@ def VLD4q8_UPD : VLD4DWB<0b0001, 0b0000, "8">;
|
||||
def VLD4q16_UPD : VLD4DWB<0b0001, 0b0100, "16">;
|
||||
def VLD4q32_UPD : VLD4DWB<0b0001, 0b1000, "32">;
|
||||
|
||||
def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo;
|
||||
def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo;
|
||||
def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo;
|
||||
|
||||
// ...alternate versions to be allocated odd register numbers:
|
||||
def VLD4q8odd_UPD : VLD4DWB<0b0001, 0b0000, "8">;
|
||||
def VLD4q16odd_UPD : VLD4DWB<0b0001, 0b0100, "16">;
|
||||
def VLD4q32odd_UPD : VLD4DWB<0b0001, 0b1000, "32">;
|
||||
def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo;
|
||||
def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo;
|
||||
def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo;
|
||||
|
||||
// VLD1LN : Vector Load (single element to one lane)
|
||||
// FIXME: Not yet implemented.
|
||||
|
||||
@ -74,10 +74,6 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
|
||||
Stride = 2;
|
||||
return true;
|
||||
|
||||
case ARM::VLD3d8:
|
||||
case ARM::VLD3d16:
|
||||
case ARM::VLD3d32:
|
||||
case ARM::VLD1d64T:
|
||||
case ARM::VLD3LNd8:
|
||||
case ARM::VLD3LNd16:
|
||||
case ARM::VLD3LNd32:
|
||||
@ -85,24 +81,6 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
|
||||
NumRegs = 3;
|
||||
return true;
|
||||
|
||||
case ARM::VLD3q8_UPD:
|
||||
case ARM::VLD3q16_UPD:
|
||||
case ARM::VLD3q32_UPD:
|
||||
FirstOpnd = 0;
|
||||
NumRegs = 3;
|
||||
Offset = 0;
|
||||
Stride = 2;
|
||||
return true;
|
||||
|
||||
case ARM::VLD3q8odd_UPD:
|
||||
case ARM::VLD3q16odd_UPD:
|
||||
case ARM::VLD3q32odd_UPD:
|
||||
FirstOpnd = 0;
|
||||
NumRegs = 3;
|
||||
Offset = 1;
|
||||
Stride = 2;
|
||||
return true;
|
||||
|
||||
case ARM::VLD3LNq16:
|
||||
case ARM::VLD3LNq32:
|
||||
FirstOpnd = 0;
|
||||
@ -119,10 +97,6 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
|
||||
Stride = 2;
|
||||
return true;
|
||||
|
||||
case ARM::VLD4d8:
|
||||
case ARM::VLD4d16:
|
||||
case ARM::VLD4d32:
|
||||
case ARM::VLD1d64Q:
|
||||
case ARM::VLD4LNd8:
|
||||
case ARM::VLD4LNd16:
|
||||
case ARM::VLD4LNd32:
|
||||
@ -130,24 +104,6 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
|
||||
NumRegs = 4;
|
||||
return true;
|
||||
|
||||
case ARM::VLD4q8_UPD:
|
||||
case ARM::VLD4q16_UPD:
|
||||
case ARM::VLD4q32_UPD:
|
||||
FirstOpnd = 0;
|
||||
NumRegs = 4;
|
||||
Offset = 0;
|
||||
Stride = 2;
|
||||
return true;
|
||||
|
||||
case ARM::VLD4q8odd_UPD:
|
||||
case ARM::VLD4q16odd_UPD:
|
||||
case ARM::VLD4q32odd_UPD:
|
||||
FirstOpnd = 0;
|
||||
NumRegs = 4;
|
||||
Offset = 1;
|
||||
Stride = 2;
|
||||
return true;
|
||||
|
||||
case ARM::VLD4LNq16:
|
||||
case ARM::VLD4LNq32:
|
||||
FirstOpnd = 0;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user