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https://github.com/c64scene-ar/llvm-6502.git
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ARM: Tidy up IntrinsicsARM.td a bit.
Make the TargetPrefix setting one big setting instead of being spread out everywhere. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164265 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
e853d2e250
commit
f5958e9dea
@ -16,147 +16,136 @@
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// TLS
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let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
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def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
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Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
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}
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def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
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Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
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//===----------------------------------------------------------------------===//
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// Saturating Arithmentic
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let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
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def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem, Commutative]>;
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def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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}
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def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem, Commutative]>;
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def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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//===----------------------------------------------------------------------===//
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// Load and Store exclusive doubleword
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let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
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def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
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llvm_ptr_ty], [IntrReadWriteArgMem]>;
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def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty],
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[IntrReadArgMem]>;
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}
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def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
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llvm_ptr_ty], [IntrReadWriteArgMem]>;
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def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty],
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[IntrReadArgMem]>;
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//===----------------------------------------------------------------------===//
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// VFP
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let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
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def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
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Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
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def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
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Intrinsic<[], [llvm_i32_ty], []>;
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def int_arm_vcvtr : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
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[IntrNoMem]>;
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def int_arm_vcvtru : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
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[IntrNoMem]>;
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}
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def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
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Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
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def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
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Intrinsic<[], [llvm_i32_ty], []>;
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def int_arm_vcvtr : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
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[IntrNoMem]>;
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def int_arm_vcvtru : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
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[IntrNoMem]>;
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//===----------------------------------------------------------------------===//
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// Coprocessor
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let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
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// Move to coprocessor
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def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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// Move to coprocessor
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def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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// Move from coprocessor
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def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty], []>;
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def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty], []>;
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// Move from coprocessor
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def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty], []>;
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def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty], []>;
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// Coprocessor data processing
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def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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// Coprocessor data processing
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def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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// Move from two registers to coprocessor
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def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty], []>;
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def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty], []>;
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}
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// Move from two registers to coprocessor
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def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty], []>;
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def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty], []>;
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//===----------------------------------------------------------------------===//
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// Advanced SIMD (NEON)
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let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
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// The following classes do not correspond directly to GCC builtins.
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class Neon_1Arg_Intrinsic
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: Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
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class Neon_1Arg_Narrow_Intrinsic
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: Intrinsic<[llvm_anyvector_ty],
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[LLVMExtendedElementVectorType<0>], [IntrNoMem]>;
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class Neon_2Arg_Intrinsic
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: Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem]>;
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class Neon_2Arg_Narrow_Intrinsic
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: Intrinsic<[llvm_anyvector_ty],
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[LLVMExtendedElementVectorType<0>,
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LLVMExtendedElementVectorType<0>],
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[IntrNoMem]>;
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class Neon_2Arg_Long_Intrinsic
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: Intrinsic<[llvm_anyvector_ty],
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[LLVMTruncatedElementVectorType<0>,
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LLVMTruncatedElementVectorType<0>],
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[IntrNoMem]>;
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class Neon_3Arg_Intrinsic
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: Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem]>;
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class Neon_3Arg_Long_Intrinsic
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: Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>,
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LLVMTruncatedElementVectorType<0>,
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LLVMTruncatedElementVectorType<0>],
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[IntrNoMem]>;
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class Neon_CvtFxToFP_Intrinsic
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: Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
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class Neon_CvtFPToFx_Intrinsic
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: Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
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// The following classes do not correspond directly to GCC builtins.
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class Neon_1Arg_Intrinsic
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: Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
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class Neon_1Arg_Narrow_Intrinsic
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: Intrinsic<[llvm_anyvector_ty],
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[LLVMExtendedElementVectorType<0>], [IntrNoMem]>;
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class Neon_2Arg_Intrinsic
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: Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem]>;
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class Neon_2Arg_Narrow_Intrinsic
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: Intrinsic<[llvm_anyvector_ty],
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[LLVMExtendedElementVectorType<0>,
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LLVMExtendedElementVectorType<0>],
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[IntrNoMem]>;
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class Neon_2Arg_Long_Intrinsic
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: Intrinsic<[llvm_anyvector_ty],
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[LLVMTruncatedElementVectorType<0>,
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LLVMTruncatedElementVectorType<0>],
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[IntrNoMem]>;
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class Neon_3Arg_Intrinsic
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: Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem]>;
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class Neon_3Arg_Long_Intrinsic
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: Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>,
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LLVMTruncatedElementVectorType<0>,
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LLVMTruncatedElementVectorType<0>],
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[IntrNoMem]>;
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class Neon_CvtFxToFP_Intrinsic
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: Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
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class Neon_CvtFPToFx_Intrinsic
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: Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
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// The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
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// Besides the table, VTBL has one other v8i8 argument and VTBX has two.
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// Overall, the classes range from 2 to 6 v8i8 arguments.
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class Neon_Tbl2Arg_Intrinsic
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: Intrinsic<[llvm_v8i8_ty],
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[llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
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class Neon_Tbl3Arg_Intrinsic
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: Intrinsic<[llvm_v8i8_ty],
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[llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
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class Neon_Tbl4Arg_Intrinsic
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: Intrinsic<[llvm_v8i8_ty],
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[llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
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[IntrNoMem]>;
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class Neon_Tbl5Arg_Intrinsic
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: Intrinsic<[llvm_v8i8_ty],
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[llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
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llvm_v8i8_ty], [IntrNoMem]>;
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class Neon_Tbl6Arg_Intrinsic
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: Intrinsic<[llvm_v8i8_ty],
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[llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
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llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
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}
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// The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
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// Besides the table, VTBL has one other v8i8 argument and VTBX has two.
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// Overall, the classes range from 2 to 6 v8i8 arguments.
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class Neon_Tbl2Arg_Intrinsic
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: Intrinsic<[llvm_v8i8_ty],
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[llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
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class Neon_Tbl3Arg_Intrinsic
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: Intrinsic<[llvm_v8i8_ty],
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[llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
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class Neon_Tbl4Arg_Intrinsic
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: Intrinsic<[llvm_v8i8_ty],
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[llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
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[IntrNoMem]>;
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class Neon_Tbl5Arg_Intrinsic
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: Intrinsic<[llvm_v8i8_ty],
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[llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
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llvm_v8i8_ty], [IntrNoMem]>;
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class Neon_Tbl6Arg_Intrinsic
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: Intrinsic<[llvm_v8i8_ty],
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[llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
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llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
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// Arithmetic ops
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@ -209,20 +198,18 @@ def int_arm_neon_vsubhn : Neon_2Arg_Narrow_Intrinsic;
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def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
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// Vector Absolute Compare.
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let TargetPrefix = "arm" in {
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def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty],
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[llvm_v2f32_ty, llvm_v2f32_ty],
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[IntrNoMem]>;
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def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty],
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[llvm_v4f32_ty, llvm_v4f32_ty],
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[IntrNoMem]>;
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def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty],
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[llvm_v2f32_ty, llvm_v2f32_ty],
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[IntrNoMem]>;
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def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty],
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[llvm_v4f32_ty, llvm_v4f32_ty],
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[IntrNoMem]>;
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}
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def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty],
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[llvm_v2f32_ty, llvm_v2f32_ty],
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[IntrNoMem]>;
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def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty],
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[llvm_v4f32_ty, llvm_v4f32_ty],
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[IntrNoMem]>;
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def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty],
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[llvm_v2f32_ty, llvm_v2f32_ty],
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[IntrNoMem]>;
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def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty],
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[llvm_v4f32_ty, llvm_v4f32_ty],
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[IntrNoMem]>;
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// Vector Absolute Differences.
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def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
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@ -235,24 +222,20 @@ def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
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// Note: This is different than the other "long" NEON intrinsics because
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// the result vector has half as many elements as the source vector.
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// The source and destination vector types must be specified separately.
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let TargetPrefix = "arm" in {
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def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
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[IntrNoMem]>;
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def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
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[IntrNoMem]>;
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}
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def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
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[IntrNoMem]>;
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def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
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[IntrNoMem]>;
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// Vector Pairwise Add and Accumulate Long.
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// Note: This is similar to vpaddl but the destination vector also appears
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// as the first argument.
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let TargetPrefix = "arm" in {
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def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, llvm_anyvector_ty],
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[IntrNoMem]>;
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def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, llvm_anyvector_ty],
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[IntrNoMem]>;
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}
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def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, llvm_anyvector_ty],
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[IntrNoMem]>;
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def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, llvm_anyvector_ty],
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[IntrNoMem]>;
|
||||
|
||||
// Vector Pairwise Maximum and Minimum.
|
||||
def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
|
||||
@ -364,79 +347,78 @@ def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
|
||||
def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
|
||||
def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
|
||||
|
||||
let TargetPrefix = "arm" in {
|
||||
// De-interleaving vector loads from N-element structures.
|
||||
// Source operands are the address and alignment.
|
||||
def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
|
||||
[llvm_ptr_ty, llvm_i32_ty],
|
||||
[IntrReadArgMem]>;
|
||||
def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
|
||||
[llvm_ptr_ty, llvm_i32_ty],
|
||||
[IntrReadArgMem]>;
|
||||
def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
|
||||
LLVMMatchType<0>],
|
||||
[llvm_ptr_ty, llvm_i32_ty],
|
||||
[IntrReadArgMem]>;
|
||||
def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
|
||||
LLVMMatchType<0>, LLVMMatchType<0>],
|
||||
[llvm_ptr_ty, llvm_i32_ty],
|
||||
[IntrReadArgMem]>;
|
||||
|
||||
// De-interleaving vector loads from N-element structures.
|
||||
// Source operands are the address and alignment.
|
||||
def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
|
||||
[llvm_ptr_ty, llvm_i32_ty],
|
||||
[IntrReadArgMem]>;
|
||||
def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
|
||||
[llvm_ptr_ty, llvm_i32_ty],
|
||||
[IntrReadArgMem]>;
|
||||
def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
|
||||
LLVMMatchType<0>],
|
||||
[llvm_ptr_ty, llvm_i32_ty],
|
||||
[IntrReadArgMem]>;
|
||||
def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
|
||||
LLVMMatchType<0>, LLVMMatchType<0>],
|
||||
[llvm_ptr_ty, llvm_i32_ty],
|
||||
[IntrReadArgMem]>;
|
||||
// Vector load N-element structure to one lane.
|
||||
// Source operands are: the address, the N input vectors (since only one
|
||||
// lane is assigned), the lane number, and the alignment.
|
||||
def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
|
||||
[llvm_ptr_ty, LLVMMatchType<0>,
|
||||
LLVMMatchType<0>, llvm_i32_ty,
|
||||
llvm_i32_ty], [IntrReadArgMem]>;
|
||||
def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
|
||||
LLVMMatchType<0>],
|
||||
[llvm_ptr_ty, LLVMMatchType<0>,
|
||||
LLVMMatchType<0>, LLVMMatchType<0>,
|
||||
llvm_i32_ty, llvm_i32_ty],
|
||||
[IntrReadArgMem]>;
|
||||
def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
|
||||
LLVMMatchType<0>, LLVMMatchType<0>],
|
||||
[llvm_ptr_ty, LLVMMatchType<0>,
|
||||
LLVMMatchType<0>, LLVMMatchType<0>,
|
||||
LLVMMatchType<0>, llvm_i32_ty,
|
||||
llvm_i32_ty], [IntrReadArgMem]>;
|
||||
|
||||
// Vector load N-element structure to one lane.
|
||||
// Source operands are: the address, the N input vectors (since only one
|
||||
// lane is assigned), the lane number, and the alignment.
|
||||
def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
|
||||
[llvm_ptr_ty, LLVMMatchType<0>,
|
||||
LLVMMatchType<0>, llvm_i32_ty,
|
||||
llvm_i32_ty], [IntrReadArgMem]>;
|
||||
def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
|
||||
LLVMMatchType<0>],
|
||||
[llvm_ptr_ty, LLVMMatchType<0>,
|
||||
LLVMMatchType<0>, LLVMMatchType<0>,
|
||||
llvm_i32_ty, llvm_i32_ty],
|
||||
[IntrReadArgMem]>;
|
||||
def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
|
||||
LLVMMatchType<0>, LLVMMatchType<0>],
|
||||
[llvm_ptr_ty, LLVMMatchType<0>,
|
||||
LLVMMatchType<0>, LLVMMatchType<0>,
|
||||
LLVMMatchType<0>, llvm_i32_ty,
|
||||
llvm_i32_ty], [IntrReadArgMem]>;
|
||||
// Interleaving vector stores from N-element structures.
|
||||
// Source operands are: the address, the N vectors, and the alignment.
|
||||
def int_arm_neon_vst1 : Intrinsic<[],
|
||||
[llvm_ptr_ty, llvm_anyvector_ty,
|
||||
llvm_i32_ty], [IntrReadWriteArgMem]>;
|
||||
def int_arm_neon_vst2 : Intrinsic<[],
|
||||
[llvm_ptr_ty, llvm_anyvector_ty,
|
||||
LLVMMatchType<0>, llvm_i32_ty],
|
||||
[IntrReadWriteArgMem]>;
|
||||
def int_arm_neon_vst3 : Intrinsic<[],
|
||||
[llvm_ptr_ty, llvm_anyvector_ty,
|
||||
LLVMMatchType<0>, LLVMMatchType<0>,
|
||||
llvm_i32_ty], [IntrReadWriteArgMem]>;
|
||||
def int_arm_neon_vst4 : Intrinsic<[],
|
||||
[llvm_ptr_ty, llvm_anyvector_ty,
|
||||
LLVMMatchType<0>, LLVMMatchType<0>,
|
||||
LLVMMatchType<0>, llvm_i32_ty],
|
||||
[IntrReadWriteArgMem]>;
|
||||
|
||||
// Interleaving vector stores from N-element structures.
|
||||
// Source operands are: the address, the N vectors, and the alignment.
|
||||
def int_arm_neon_vst1 : Intrinsic<[],
|
||||
[llvm_ptr_ty, llvm_anyvector_ty,
|
||||
llvm_i32_ty], [IntrReadWriteArgMem]>;
|
||||
def int_arm_neon_vst2 : Intrinsic<[],
|
||||
[llvm_ptr_ty, llvm_anyvector_ty,
|
||||
LLVMMatchType<0>, llvm_i32_ty],
|
||||
[IntrReadWriteArgMem]>;
|
||||
def int_arm_neon_vst3 : Intrinsic<[],
|
||||
[llvm_ptr_ty, llvm_anyvector_ty,
|
||||
LLVMMatchType<0>, LLVMMatchType<0>,
|
||||
llvm_i32_ty], [IntrReadWriteArgMem]>;
|
||||
def int_arm_neon_vst4 : Intrinsic<[],
|
||||
[llvm_ptr_ty, llvm_anyvector_ty,
|
||||
LLVMMatchType<0>, LLVMMatchType<0>,
|
||||
LLVMMatchType<0>, llvm_i32_ty],
|
||||
[IntrReadWriteArgMem]>;
|
||||
// Vector store N-element structure from one lane.
|
||||
// Source operands are: the address, the N vectors, the lane number, and
|
||||
// the alignment.
|
||||
def int_arm_neon_vst2lane : Intrinsic<[],
|
||||
[llvm_ptr_ty, llvm_anyvector_ty,
|
||||
LLVMMatchType<0>, llvm_i32_ty,
|
||||
llvm_i32_ty], [IntrReadWriteArgMem]>;
|
||||
def int_arm_neon_vst3lane : Intrinsic<[],
|
||||
[llvm_ptr_ty, llvm_anyvector_ty,
|
||||
LLVMMatchType<0>, LLVMMatchType<0>,
|
||||
llvm_i32_ty, llvm_i32_ty],
|
||||
[IntrReadWriteArgMem]>;
|
||||
def int_arm_neon_vst4lane : Intrinsic<[],
|
||||
[llvm_ptr_ty, llvm_anyvector_ty,
|
||||
LLVMMatchType<0>, LLVMMatchType<0>,
|
||||
LLVMMatchType<0>, llvm_i32_ty,
|
||||
llvm_i32_ty], [IntrReadWriteArgMem]>;
|
||||
|
||||
// Vector store N-element structure from one lane.
|
||||
// Source operands are: the address, the N vectors, the lane number, and
|
||||
// the alignment.
|
||||
def int_arm_neon_vst2lane : Intrinsic<[],
|
||||
[llvm_ptr_ty, llvm_anyvector_ty,
|
||||
LLVMMatchType<0>, llvm_i32_ty,
|
||||
llvm_i32_ty], [IntrReadWriteArgMem]>;
|
||||
def int_arm_neon_vst3lane : Intrinsic<[],
|
||||
[llvm_ptr_ty, llvm_anyvector_ty,
|
||||
LLVMMatchType<0>, LLVMMatchType<0>,
|
||||
llvm_i32_ty, llvm_i32_ty],
|
||||
[IntrReadWriteArgMem]>;
|
||||
def int_arm_neon_vst4lane : Intrinsic<[],
|
||||
[llvm_ptr_ty, llvm_anyvector_ty,
|
||||
LLVMMatchType<0>, LLVMMatchType<0>,
|
||||
LLVMMatchType<0>, llvm_i32_ty,
|
||||
llvm_i32_ty], [IntrReadWriteArgMem]>;
|
||||
}
|
||||
} // end TargetPrefix
|
||||
|
||||
Loading…
Reference in New Issue
Block a user