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Add support for the R and Q constraints.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137217 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2011-08-10 16:26:42 +00:00
parent 21ab6c066d
commit f5ade5d39a
2 changed files with 39 additions and 2 deletions
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24
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -469,14 +469,34 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
return false;
}
case 'R': // The most significant register of a pair.
case 'Q': { // The least significant register of a pair.
if (OpNum == 0)
return true;
const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
if (!FlagsOP.isImm())
return true;
unsigned Flags = FlagsOP.getImm();
unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
if (NumVals != 2)
return true;
unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
if (RegOp >= MI->getNumOperands())
return true;
const MachineOperand &MO = MI->getOperand(RegOp);
if (!MO.isReg())
return true;
unsigned Reg = MO.getReg();
O << ARMInstPrinter::getRegisterName(Reg);
return false;
}
// These modifiers are not yet supported.
case 'p': // The high single-precision register of a VFP double-precision
// register.
case 'e': // The low doubleword register of a NEON quad register.
case 'f': // The high doubleword register of a NEON quad register.
case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
case 'Q': // The least significant register of a pair.
case 'R': // The most significant register of a pair.
case 'H': // The highest-numbered register of a pair.
return true;
}

17
test/CodeGen/ARM/inlineasm4.ll Normal file
View File

@ -0,0 +1,17 @@
; RUN: llc < %s -march=arm | FileCheck %s
define double @f(double %x) {
entry:
%0 = tail call double asm "mov ${0:R}, #4\0A", "=&r"()
ret double %0
; CHECK: f:
; CHECK: mov r1, #4
}
define double @g(double %x) {
entry:
%0 = tail call double asm "mov ${0:Q}, #4\0A", "=&r"()
ret double %0
; CHECK: g:
; CHECK: mov r0, #4
}