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Rename ConstantSDNode::getValue to getZExtValue, for consistency
with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -560,7 +560,7 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) {
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case ISD::CALLSEQ_START:
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case ISD::CALLSEQ_END: {
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int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
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int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
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unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
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IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
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SDValue N0 = N->getOperand(0);
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@@ -66,7 +66,7 @@ let PrintMethod = "printCallOperand" in
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def is32ones : PatLeaf<(i64 imm), [{
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// is32ones predicate - True if the immediate is 0x00000000FFFFFFFF
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// Used to create ZXT4s appropriately
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uint64_t v = (uint64_t)N->getValue();
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uint64_t v = (uint64_t)N->getZExtValue();
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return (v == 0x00000000FFFFFFFFLL);
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}]>;
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@@ -75,36 +75,36 @@ def is32ones : PatLeaf<(i64 imm), [{
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// etc, through 0x00000000FFFFFFFF
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// Used to test for the suitability of mix*
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def isMIX1Lable: PatLeaf<(i64 imm), [{
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return((uint64_t)N->getValue()==0xFF00FF00FF00FF00LL);
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return((uint64_t)N->getZExtValue()==0xFF00FF00FF00FF00LL);
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}]>;
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def isMIX1Rable: PatLeaf<(i64 imm), [{
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return((uint64_t)N->getValue()==0x00FF00FF00FF00FFLL);
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return((uint64_t)N->getZExtValue()==0x00FF00FF00FF00FFLL);
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}]>;
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def isMIX2Lable: PatLeaf<(i64 imm), [{
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return((uint64_t)N->getValue()==0xFFFF0000FFFF0000LL);
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return((uint64_t)N->getZExtValue()==0xFFFF0000FFFF0000LL);
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}]>;
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def isMIX2Rable: PatLeaf<(i64 imm), [{
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return((uint64_t)N->getValue()==0x0000FFFF0000FFFFLL);
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return((uint64_t)N->getZExtValue()==0x0000FFFF0000FFFFLL);
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}]>;
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def isMIX4Lable: PatLeaf<(i64 imm), [{
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return((uint64_t)N->getValue()==0xFFFFFFFF00000000LL);
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return((uint64_t)N->getZExtValue()==0xFFFFFFFF00000000LL);
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}]>;
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def isMIX4Rable: PatLeaf<(i64 imm), [{
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return((uint64_t)N->getValue()==0x00000000FFFFFFFFLL);
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return((uint64_t)N->getZExtValue()==0x00000000FFFFFFFFLL);
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}]>;
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def isSHLADDimm: PatLeaf<(i64 imm), [{
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// isSHLADDimm predicate - True if the immediate is exactly 1, 2, 3 or 4
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// - 0 is *not* okay.
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// Used to create shladd instructions appropriately
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int64_t v = (int64_t)N->getValue();
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int64_t v = (int64_t)N->getZExtValue();
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return (v >= 1 && v <= 4);
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}]>;
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def immSExt14 : PatLeaf<(i64 imm), [{
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// immSExt14 predicate - True if the immediate fits in a 14-bit sign extended
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// field. Used by instructions like 'adds'.
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int64_t v = (int64_t)N->getValue();
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int64_t v = (int64_t)N->getZExtValue();
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return (v <= 8191 && v >= -8192);
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}]>;
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