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more formatting improvements, no functionality change.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79167 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2009-08-16 02:45:18 +00:00
parent d8638babf9
commit f5af556c18
1 changed files with 63 additions and 55 deletions
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118
lib/Target/X86/X86CodeEmitter.cpp
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@ -39,7 +39,7 @@ using namespace llvm;
STATISTIC(NumEmitted, "Number of machine instructions emitted"); STATISTIC(NumEmitted, "Number of machine instructions emitted");
namespace { namespace {
template<class CodeEmitter> template<class CodeEmitter>
class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass { class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
const X86InstrInfo *II; const X86InstrInfo *II;
const TargetData *TD; const TargetData *TD;
@ -103,7 +103,7 @@ template<class CodeEmitter>
template<class CodeEmitter> template<class CodeEmitter>
char Emitter<CodeEmitter>::ID = 0; char Emitter<CodeEmitter>::ID = 0;
} } // end anonymous namespace.
/// createX86CodeEmitterPass - Return a pass that emits the collected X86 code /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
/// to the specified templated MachineCodeEmitter object. /// to the specified templated MachineCodeEmitter object.
@ -352,8 +352,8 @@ void Emitter<CodeEmitter>::emitDisplacementField(const MachineOperand *RelocOp,
template<class CodeEmitter> template<class CodeEmitter>
void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI, void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI,
unsigned Op, unsigned RegOpcodeField, unsigned Op,unsigned RegOpcodeField,
intptr_t PCAdj) { intptr_t PCAdj) {
const MachineOperand &Op3 = MI.getOperand(Op+3); const MachineOperand &Op3 = MI.getOperand(Op+3);
int DispVal = 0; int DispVal = 0;
const MachineOperand *DispForReloc = 0; const MachineOperand *DispForReloc = 0;
@ -477,9 +477,8 @@ void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI,
} }
template<class CodeEmitter> template<class CodeEmitter>
void Emitter<CodeEmitter>::emitInstruction( void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI,
const MachineInstr &MI, const TargetInstrDesc *Desc) {
const TargetInstrDesc *Desc) {
DEBUG(errs() << MI); DEBUG(errs() << MI);
MCE.processDebugLoc(MI.getDebugLoc()); MCE.processDebugLoc(MI.getDebugLoc());
@ -487,7 +486,8 @@ void Emitter<CodeEmitter>::emitInstruction(
unsigned Opcode = Desc->Opcode; unsigned Opcode = Desc->Opcode;
// Emit the lock opcode prefix as needed. // Emit the lock opcode prefix as needed.
if (Desc->TSFlags & X86II::LOCK) MCE.emitByte(0xF0); if (Desc->TSFlags & X86II::LOCK)
MCE.emitByte(0xF0);
// Emit segment override opcode prefix as needed. // Emit segment override opcode prefix as needed.
switch (Desc->TSFlags & X86II::SegOvrMask) { switch (Desc->TSFlags & X86II::SegOvrMask) {
@ -502,13 +502,16 @@ void Emitter<CodeEmitter>::emitInstruction(
} }
// Emit the repeat opcode prefix as needed. // Emit the repeat opcode prefix as needed.
if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3); if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP)
MCE.emitByte(0xF3);
// Emit the operand size opcode prefix as needed. // Emit the operand size opcode prefix as needed.
if (Desc->TSFlags & X86II::OpSize) MCE.emitByte(0x66); if (Desc->TSFlags & X86II::OpSize)
MCE.emitByte(0x66);
// Emit the address size opcode prefix as needed. // Emit the address size opcode prefix as needed.
if (Desc->TSFlags & X86II::AdSize) MCE.emitByte(0x67); if (Desc->TSFlags & X86II::AdSize)
MCE.emitByte(0x67);
bool Need0FPrefix = false; bool Need0FPrefix = false;
switch (Desc->TSFlags & X86II::Op0Mask) { switch (Desc->TSFlags & X86II::Op0Mask) {
@ -540,10 +543,9 @@ void Emitter<CodeEmitter>::emitInstruction(
case 0: break; // No prefix! case 0: break; // No prefix!
} }
// Handle REX prefix.
if (Is64BitMode) { if (Is64BitMode) {
// REX prefix if (unsigned REX = X86InstrInfo::determineREX(MI))
unsigned REX = X86InstrInfo::determineREX(MI);
if (REX)
MCE.emitByte(0x40 | REX); MCE.emitByte(0x40 | REX);
} }
@ -552,8 +554,8 @@ void Emitter<CodeEmitter>::emitInstruction(
MCE.emitByte(0x0F); MCE.emitByte(0x0F);
switch (Desc->TSFlags & X86II::Op0Mask) { switch (Desc->TSFlags & X86II::Op0Mask) {
case X86II::TF: // F2 0F 38 case X86II::TF: // F2 0F 38
case X86II::T8: // 0F 38 case X86II::T8: // 0F 38
MCE.emitByte(0x38); MCE.emitByte(0x38);
break; break;
case X86II::TA: // 0F 3A case X86II::TA: // 0F 3A
@ -582,14 +584,12 @@ void Emitter<CodeEmitter>::emitInstruction(
llvm_unreachable("psuedo instructions should be removed before code" llvm_unreachable("psuedo instructions should be removed before code"
" emission"); " emission");
break; break;
case TargetInstrInfo::INLINEASM: { case TargetInstrInfo::INLINEASM:
// We allow inline assembler nodes with empty bodies - they can // We allow inline assembler nodes with empty bodies - they can
// implicitly define registers, which is ok for JIT. // implicitly define registers, which is ok for JIT.
if (MI.getOperand(0).getSymbolName()[0]) { assert(MI.getOperand(0).getSymbolName()[0] == 0 &&
llvm_report_error("JIT does not support inline asm!"); "JIT does not support inline asm!");
}
break; break;
}
case TargetInstrInfo::DBG_LABEL: case TargetInstrInfo::DBG_LABEL:
case TargetInstrInfo::EH_LABEL: case TargetInstrInfo::EH_LABEL:
MCE.emitLabel(MI.getOperand(0).getImm()); MCE.emitLabel(MI.getOperand(0).getImm());
@ -612,45 +612,53 @@ void Emitter<CodeEmitter>::emitInstruction(
} }
CurOp = NumOps; CurOp = NumOps;
break; break;
case X86II::RawFrm: case X86II::RawFrm: {
MCE.emitByte(BaseOpcode); MCE.emitByte(BaseOpcode);
if (CurOp != NumOps) { if (CurOp == NumOps)
const MachineOperand &MO = MI.getOperand(CurOp++); break;
const MachineOperand &MO = MI.getOperand(CurOp++);
DEBUG(errs() << "RawFrm CurOp " << CurOp << "\n"); DEBUG(errs() << "RawFrm CurOp " << CurOp << "\n");
DEBUG(errs() << "isMBB " << MO.isMBB() << "\n"); DEBUG(errs() << "isMBB " << MO.isMBB() << "\n");
DEBUG(errs() << "isGlobal " << MO.isGlobal() << "\n"); DEBUG(errs() << "isGlobal " << MO.isGlobal() << "\n");
DEBUG(errs() << "isSymbol " << MO.isSymbol() << "\n"); DEBUG(errs() << "isSymbol " << MO.isSymbol() << "\n");
DEBUG(errs() << "isImm " << MO.isImm() << "\n"); DEBUG(errs() << "isImm " << MO.isImm() << "\n");
if (MO.isMBB()) { if (MO.isMBB()) {
emitPCRelativeBlockAddress(MO.getMBB()); emitPCRelativeBlockAddress(MO.getMBB());
} else if (MO.isGlobal()) { break;
// Assume undefined functions may be outside the Small codespace.
bool NeedStub =
(Is64BitMode &&
(TM.getCodeModel() == CodeModel::Large ||
TM.getSubtarget<X86Subtarget>().isTargetDarwin())) ||
Opcode == X86::TAILJMPd;
emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
MO.getOffset(), 0, NeedStub);
} else if (MO.isSymbol()) {
emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
} else if (MO.isImm()) {
if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32) {
// Fix up immediate operand for pc relative calls.
intptr_t Imm = (intptr_t)MO.getImm();
Imm = Imm - MCE.getCurrentPCValue() - 4;
emitConstant(Imm, X86InstrInfo::sizeOfImm(Desc));
} else
emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
} else {
llvm_unreachable("Unknown RawFrm operand!");
}
} }
if (MO.isGlobal()) {
// Assume undefined functions may be outside the Small codespace.
bool NeedStub =
(Is64BitMode &&
(TM.getCodeModel() == CodeModel::Large ||
TM.getSubtarget<X86Subtarget>().isTargetDarwin())) ||
Opcode == X86::TAILJMPd;
emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
MO.getOffset(), 0, NeedStub);
break;
}
if (MO.isSymbol()) {
emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
break;
}
assert(MO.isImm() && "Unknown RawFrm operand!");
if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32) {
// Fix up immediate operand for pc relative calls.
intptr_t Imm = (intptr_t)MO.getImm();
Imm = Imm - MCE.getCurrentPCValue() - 4;
emitConstant(Imm, X86InstrInfo::sizeOfImm(Desc));
} else
emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
break; break;
}
case X86II::AddRegFrm: { case X86II::AddRegFrm: {
MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg())); MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
@ -846,7 +854,7 @@ void Emitter<CodeEmitter>::emitInstruction(
if (!Desc->isVariadic() && CurOp != NumOps) { if (!Desc->isVariadic() && CurOp != NumOps) {
#ifndef NDEBUG #ifndef NDEBUG
errs() << "Cannot encode: " << MI << "\n"; errs() << "Cannot encode all operands of: " << MI << "\n";
#endif #endif
llvm_unreachable(0); llvm_unreachable(0);
} }