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https://github.com/c64scene-ar/llvm-6502.git
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- Add support for the rest of AVX SSE3 instructions
- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M represents a REX equivalent two byte leading opcode git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107523 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
65766ce7df
commit
f5cd8c51e3
@ -3380,6 +3380,18 @@ multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
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(bitconvert (mem_frag128 addr:$src))))]>, OpSize;
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}
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let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in {
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defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv8i8, memopv16i8,
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int_x86_ssse3_pabs_b,
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int_x86_ssse3_pabs_b_128>, VEX;
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defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv4i16, memopv8i16,
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int_x86_ssse3_pabs_w,
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int_x86_ssse3_pabs_w_128>, VEX;
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defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv2i32, memopv4i32,
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int_x86_ssse3_pabs_d,
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int_x86_ssse3_pabs_d_128>, VEX;
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}
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defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv8i8, memopv16i8,
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int_x86_ssse3_pabs_b,
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int_x86_ssse3_pabs_b_128>;
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@ -3433,6 +3445,47 @@ multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
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(bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
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}
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let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in {
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let isCommutable = 0 in {
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defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv4i16, memopv8i16,
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int_x86_ssse3_phadd_w,
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int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
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defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv2i32, memopv4i32,
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int_x86_ssse3_phadd_d,
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int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
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defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv4i16, memopv8i16,
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int_x86_ssse3_phadd_sw,
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int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
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defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv4i16, memopv8i16,
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int_x86_ssse3_phsub_w,
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int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
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defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv2i32, memopv4i32,
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int_x86_ssse3_phsub_d,
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int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
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defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv4i16, memopv8i16,
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int_x86_ssse3_phsub_sw,
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int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
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defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv8i8, memopv16i8,
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int_x86_ssse3_pmadd_ub_sw,
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int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
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defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv8i8, memopv16i8,
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int_x86_ssse3_pshuf_b,
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int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
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defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv8i8, memopv16i8,
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int_x86_ssse3_psign_b,
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int_x86_ssse3_psign_b_128, 0>, VEX_4V;
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defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv4i16, memopv8i16,
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int_x86_ssse3_psign_w,
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int_x86_ssse3_psign_w_128, 0>, VEX_4V;
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defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv2i32, memopv4i32,
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int_x86_ssse3_psign_d,
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int_x86_ssse3_psign_d_128, 0>, VEX_4V;
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}
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defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv4i16, memopv8i16,
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int_x86_ssse3_pmul_hr_sw,
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int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
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}
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// None of these have i8 immediate fields.
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let ImmT = NoImm, Constraints = "$src1 = $dst" in {
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let isCommutable = 0 in {
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@ -3484,26 +3537,43 @@ def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
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// SSSE3 - Packed Align Instruction Patterns
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//===---------------------------------------------------------------------===//
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let Constraints = "$src1 = $dst" in {
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def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2, i8imm:$src3),
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"palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[]>;
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def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2, i8imm:$src3),
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"palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[]>;
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multiclass sse3_palign<string asm, bit Is2Addr = 1> {
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def R64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2, i8imm:$src3),
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!if(Is2Addr,
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!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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!strconcat(asm,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
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[]>;
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def R64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2, i8imm:$src3),
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!if(Is2Addr,
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!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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!strconcat(asm,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
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[]>;
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def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, i8imm:$src3),
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"palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[]>, OpSize;
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def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, i8imm:$src3),
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"palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[]>, OpSize;
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def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, i8imm:$src3),
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!if(Is2Addr,
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!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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!strconcat(asm,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
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[]>, OpSize;
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def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, i8imm:$src3),
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!if(Is2Addr,
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!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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!strconcat(asm,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
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[]>, OpSize;
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}
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let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in
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defm VPALIGN : sse3_palign<"vpalignr", 0>, VEX_4V;
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let Constraints = "$src1 = $dst" in
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defm PALIGN : sse3_palign<"palignr">;
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let AddedComplexity = 5 in {
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def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)),
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@ -543,7 +543,7 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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//
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unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
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if (VEX_B && VEX_X && !VEX_W) { // 2 byte VEX prefix
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if (VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) { // 2 byte VEX prefix
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EmitByte(0xC5, CurByte, OS);
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EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
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return;
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@ -11614,3 +11614,131 @@
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// CHECK: encoding: [0xc5,0xe9,0x7d,0x18]
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vhsubpd (%eax), %xmm2, %xmm3
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// CHECK: vpabsb %xmm1, %xmm2
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// CHECK: encoding: [0xc4,0xe2,0x79,0x1c,0xd1]
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vpabsb %xmm1, %xmm2
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// CHECK: vpabsb (%eax), %xmm2
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// CHECK: encoding: [0xc4,0xe2,0x79,0x1c,0x10]
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vpabsb (%eax), %xmm2
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// CHECK: vpabsw %xmm1, %xmm2
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// CHECK: encoding: [0xc4,0xe2,0x79,0x1d,0xd1]
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vpabsw %xmm1, %xmm2
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// CHECK: vpabsw (%eax), %xmm2
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// CHECK: encoding: [0xc4,0xe2,0x79,0x1d,0x10]
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vpabsw (%eax), %xmm2
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// CHECK: vpabsd %xmm1, %xmm2
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// CHECK: encoding: [0xc4,0xe2,0x79,0x1e,0xd1]
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vpabsd %xmm1, %xmm2
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// CHECK: vpabsd (%eax), %xmm2
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// CHECK: encoding: [0xc4,0xe2,0x79,0x1e,0x10]
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vpabsd (%eax), %xmm2
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// CHECK: vphaddw %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe2,0x69,0x01,0xd9]
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vphaddw %xmm1, %xmm2, %xmm3
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// CHECK: vphaddw (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe2,0x69,0x01,0x18]
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vphaddw (%eax), %xmm2, %xmm3
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// CHECK: vphaddd %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe2,0x69,0x02,0xd9]
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vphaddd %xmm1, %xmm2, %xmm3
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// CHECK: vphaddd (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe2,0x69,0x02,0x18]
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vphaddd (%eax), %xmm2, %xmm3
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// CHECK: vphaddsw %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe2,0x69,0x03,0xd9]
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vphaddsw %xmm1, %xmm2, %xmm3
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// CHECK: vphaddsw (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe2,0x69,0x03,0x18]
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vphaddsw (%eax), %xmm2, %xmm3
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// CHECK: vphsubw %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe2,0x69,0x05,0xd9]
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vphsubw %xmm1, %xmm2, %xmm3
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// CHECK: vphsubw (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe2,0x69,0x05,0x18]
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vphsubw (%eax), %xmm2, %xmm3
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// CHECK: vphsubd %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe2,0x69,0x06,0xd9]
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vphsubd %xmm1, %xmm2, %xmm3
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// CHECK: vphsubd (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe2,0x69,0x06,0x18]
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vphsubd (%eax), %xmm2, %xmm3
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// CHECK: vphsubsw %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe2,0x69,0x07,0xd9]
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vphsubsw %xmm1, %xmm2, %xmm3
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// CHECK: vphsubsw (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe2,0x69,0x07,0x18]
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vphsubsw (%eax), %xmm2, %xmm3
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// CHECK: vpmaddubsw %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe2,0x69,0x04,0xd9]
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vpmaddubsw %xmm1, %xmm2, %xmm3
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// CHECK: vpmaddubsw (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe2,0x69,0x04,0x18]
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vpmaddubsw (%eax), %xmm2, %xmm3
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// CHECK: vpshufb %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe2,0x69,0x00,0xd9]
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vpshufb %xmm1, %xmm2, %xmm3
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// CHECK: vpshufb (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe2,0x69,0x00,0x18]
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vpshufb (%eax), %xmm2, %xmm3
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// CHECK: vpsignb %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe2,0x69,0x08,0xd9]
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vpsignb %xmm1, %xmm2, %xmm3
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// CHECK: vpsignb (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe2,0x69,0x08,0x18]
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vpsignb (%eax), %xmm2, %xmm3
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// CHECK: vpsignw %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe2,0x69,0x09,0xd9]
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vpsignw %xmm1, %xmm2, %xmm3
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// CHECK: vpsignw (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe2,0x69,0x09,0x18]
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vpsignw (%eax), %xmm2, %xmm3
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// CHECK: vpsignd %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe2,0x69,0x0a,0xd9]
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vpsignd %xmm1, %xmm2, %xmm3
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// CHECK: vpsignd (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe2,0x69,0x0a,0x18]
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vpsignd (%eax), %xmm2, %xmm3
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// CHECK: vpmulhrsw %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe2,0x69,0x0b,0xd9]
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vpmulhrsw %xmm1, %xmm2, %xmm3
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// CHECK: vpmulhrsw (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe2,0x69,0x0b,0x18]
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vpmulhrsw (%eax), %xmm2, %xmm3
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// CHECK: vpalignr $7, %xmm1, %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe3,0x69,0x0f,0xd9,0x07]
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vpalignr $7, %xmm1, %xmm2, %xmm3
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// CHECK: vpalignr $7, (%eax), %xmm2, %xmm3
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// CHECK: encoding: [0xc4,0xe3,0x69,0x0f,0x18,0x07]
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vpalignr $7, (%eax), %xmm2, %xmm3
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@ -1662,3 +1662,131 @@ pshufb CPI1_0(%rip), %xmm1
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// CHECK: encoding: [0xc5,0x19,0x7d,0x28]
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vhsubpd (%rax), %xmm12, %xmm13
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// CHECK: vpabsb %xmm11, %xmm12
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// CHECK: encoding: [0xc4,0x42,0x79,0x1c,0xe3]
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vpabsb %xmm11, %xmm12
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// CHECK: vpabsb (%rax), %xmm12
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// CHECK: encoding: [0xc4,0x62,0x79,0x1c,0x20]
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vpabsb (%rax), %xmm12
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// CHECK: vpabsw %xmm11, %xmm12
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// CHECK: encoding: [0xc4,0x42,0x79,0x1d,0xe3]
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vpabsw %xmm11, %xmm12
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// CHECK: vpabsw (%rax), %xmm12
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// CHECK: encoding: [0xc4,0x62,0x79,0x1d,0x20]
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vpabsw (%rax), %xmm12
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// CHECK: vpabsd %xmm11, %xmm12
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// CHECK: encoding: [0xc4,0x42,0x79,0x1e,0xe3]
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vpabsd %xmm11, %xmm12
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// CHECK: vpabsd (%rax), %xmm12
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// CHECK: encoding: [0xc4,0x62,0x79,0x1e,0x20]
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vpabsd (%rax), %xmm12
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// CHECK: vphaddw %xmm11, %xmm12, %xmm13
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// CHECK: encoding: [0xc4,0x42,0x19,0x01,0xeb]
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vphaddw %xmm11, %xmm12, %xmm13
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// CHECK: vphaddw (%rax), %xmm12, %xmm13
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// CHECK: encoding: [0xc4,0x62,0x19,0x01,0x28]
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vphaddw (%rax), %xmm12, %xmm13
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// CHECK: vphaddd %xmm11, %xmm12, %xmm13
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// CHECK: encoding: [0xc4,0x42,0x19,0x02,0xeb]
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vphaddd %xmm11, %xmm12, %xmm13
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// CHECK: vphaddd (%rax), %xmm12, %xmm13
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// CHECK: encoding: [0xc4,0x62,0x19,0x02,0x28]
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vphaddd (%rax), %xmm12, %xmm13
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// CHECK: vphaddsw %xmm11, %xmm12, %xmm13
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// CHECK: encoding: [0xc4,0x42,0x19,0x03,0xeb]
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vphaddsw %xmm11, %xmm12, %xmm13
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|
||||
// CHECK: vphaddsw (%rax), %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x62,0x19,0x03,0x28]
|
||||
vphaddsw (%rax), %xmm12, %xmm13
|
||||
|
||||
// CHECK: vphsubw %xmm11, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x42,0x19,0x05,0xeb]
|
||||
vphsubw %xmm11, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vphsubw (%rax), %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x62,0x19,0x05,0x28]
|
||||
vphsubw (%rax), %xmm12, %xmm13
|
||||
|
||||
// CHECK: vphsubd %xmm11, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x42,0x19,0x06,0xeb]
|
||||
vphsubd %xmm11, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vphsubd (%rax), %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x62,0x19,0x06,0x28]
|
||||
vphsubd (%rax), %xmm12, %xmm13
|
||||
|
||||
// CHECK: vphsubsw %xmm11, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x42,0x19,0x07,0xeb]
|
||||
vphsubsw %xmm11, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vphsubsw (%rax), %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x62,0x19,0x07,0x28]
|
||||
vphsubsw (%rax), %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpmaddubsw %xmm11, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x42,0x19,0x04,0xeb]
|
||||
vpmaddubsw %xmm11, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpmaddubsw (%rax), %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x62,0x19,0x04,0x28]
|
||||
vpmaddubsw (%rax), %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpshufb %xmm11, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x42,0x19,0x00,0xeb]
|
||||
vpshufb %xmm11, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpshufb (%rax), %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x62,0x19,0x00,0x28]
|
||||
vpshufb (%rax), %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpsignb %xmm11, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x42,0x19,0x08,0xeb]
|
||||
vpsignb %xmm11, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpsignb (%rax), %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x62,0x19,0x08,0x28]
|
||||
vpsignb (%rax), %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpsignw %xmm11, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x42,0x19,0x09,0xeb]
|
||||
vpsignw %xmm11, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpsignw (%rax), %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x62,0x19,0x09,0x28]
|
||||
vpsignw (%rax), %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpsignd %xmm11, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x42,0x19,0x0a,0xeb]
|
||||
vpsignd %xmm11, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpsignd (%rax), %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x62,0x19,0x0a,0x28]
|
||||
vpsignd (%rax), %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpmulhrsw %xmm11, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x42,0x19,0x0b,0xeb]
|
||||
vpmulhrsw %xmm11, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpmulhrsw (%rax), %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x62,0x19,0x0b,0x28]
|
||||
vpmulhrsw (%rax), %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpalignr $7, %xmm11, %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x43,0x19,0x0f,0xeb,0x07]
|
||||
vpalignr $7, %xmm11, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vpalignr $7, (%rax), %xmm12, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x63,0x19,0x0f,0x28,0x07]
|
||||
vpalignr $7, (%rax), %xmm12, %xmm13
|
||||
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user