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[XCore] Add missing 0r instructions.

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These instructions are not targeted by the compiler but they are
needed for the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173623 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2013-01-27 20:42:57 +00:00
parent 245b657ab6
commit f5e7e793f1
2 changed files with 95 additions and 3 deletions
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47
lib/Target/XCore/XCoreInstrInfo.td
View File

@ -924,12 +924,21 @@ def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a),
[(int_xcore_eeu GRRegs:$a)]>;
// Zero operand short
// TODO freet, ldspc, stspc, ldssr, stssr, ldsed, stsed,
// stet, getkep, getksp, setkep, getid, kret, dcall, dret,
// dentsp, drestsp
def CLRE_0R : _F0R<0b0000001101, (outs), (ins), "clre", [(int_xcore_clre)]>;
def DCALL_0R : _F0R<0b0000011100, (outs), (ins), "dcall", []>;
let Defs = [SP], Uses = [SP] in
def DENTSP_0R : _F0R<0b0001001100, (outs), (ins), "dentsp", []>;
let Defs = [SP] in
def DRESTSP_0R : _F0R<0b0001001101, (outs), (ins), "drestsp", []>;
def DRET_0R : _F0R<0b0000011110, (outs), (ins), "dret", []>;
def FREET_0R : _F0R<0b0000001111, (outs), (ins), "freet", []>;
let Defs = [R11] in {
def GETID_0R : _F0R<0b0001001110, (outs), (ins),
"get r11, id",
@ -942,12 +951,44 @@ def GETED_0R : _F0R<0b0000111110, (outs), (ins),
def GETET_0R : _F0R<0b0000111111, (outs), (ins),
"get r11, et",
[(set R11, (int_xcore_getet))]>;
def GETKEP_0R : _F0R<0b0001001111, (outs), (ins),
"get r11, kep", []>;
def GETKSP_0R : _F0R<0b0001011100, (outs), (ins),
"get r11, ksp", []>;
}
let Defs = [SP] in
def KRET_0R : _F0R<0b0000011101, (outs), (ins), "kret", []>;
let Uses = [SP], mayLoad = 1 in {
def LDET_0R : _F0R<0b0001011110, (outs), (ins), "ldw et, sp[4]", []>;
def LDSED_0R : _F0R<0b0001011101, (outs), (ins), "ldw sed, sp[3]", []>;
def LDSPC_0R : _F0R<0b0000101100, (outs), (ins), "ldw spc, sp[1]", []>;
def LDSSR_0R : _F0R<0b0000101110, (outs), (ins), "ldw ssr, sp[2]", []>;
}
let Uses=[R11] in
def SETKEP_0R : _F0R<0b0000011111, (outs), (ins), "set kep, r11", []>;
def SSYNC_0r : _F0R<0b0000001110, (outs), (ins),
"ssync",
[(int_xcore_ssync)]>;
let Uses = [SP], mayStore = 1 in {
def STET_0R : _F0R<0b0000111101, (outs), (ins), "stw et, sp[4]", []>;
def STSED_0R : _F0R<0b0000111100, (outs), (ins), "stw sed, sp[3]", []>;
def STSPC_0R : _F0R<0b0000101101, (outs), (ins), "stw spc, sp[1]", []>;
def STSSR_0R : _F0R<0b0000101111, (outs), (ins), "stw ssr, sp[2]", []>;
}
let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
hasSideEffects = 1 in
def WAITEU_0R : _F0R<0b0000001100, (outs), (ins),

51
test/MC/Disassembler/XCore/xcore.txt
View File

@ -21,6 +21,57 @@
# CHECK: waiteu
0xec 0x07
# CHECK: dcall
0xfc 0x07
# CHECK: dentsp
0xec 0x17
# CHECK: drestsp
0xed 0x17
# CHECK: dret
0xfe 0x07
# CHECK: freet
0xef 0x07
# CHECK: get r11, kep
0xef 0x17
# CHECK: get r11, ksp
0xfc 0x17
# CHECK: kret
0xfd 0x07
# CHECK: ldw et, sp[4]
0xfe 0x17
# CHECK: ldw sed, sp[3]
0xfd 0x17
# CHECK: ldw spc, sp[1]
0xec 0x0f
# CHECK: ldw ssr, sp[2]
0xee 0x0f
# CHECK: set kep, r11
0xff 0x07
# CHECK: stw et, sp[4]
0xfd 0x0f
# CHECK: stw sed, sp[3]
0xfc 0x0f
# CHECK: stw spc, sp[1]
0xed 0x0f
# CHECK: stw ssr, sp[2]
0xef 0x0f
# 1r instructions
# CHECK: msync res[r0]