6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-20 12:31:40 +00:00
Code Issues Projects Releases Wiki Activity

Another revsh pattern. rdar://9609059

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133064 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2011-06-15 17:17:48 +00:00
parent 4cb971ce1c
commit f60ceac9cd
3 changed files with 21 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/ARM/ARMInstrInfo.td
View File

@ -3029,6 +3029,10 @@ def : ARMV6Pat<(sext_inreg (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
(shl GPR:$Rm, (i32 8))), i16), (shl GPR:$Rm, (i32 8))), i16),
(REVSH GPR:$Rm)>; (REVSH GPR:$Rm)>;
def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
(and (srl GPR:$Rm, (i32 8)), 0xFF)),
(REVSH GPR:$Rm)>;
// Need the AddedComplexity or else MOVs + REV would be chosen. // Need the AddedComplexity or else MOVs + REV would be chosen.
let AddedComplexity = 5 in let AddedComplexity = 5 in
def : ARMV6Pat<(sra (bswap GPR:$Rm), (i32 16)), (REVSH GPR:$Rm)>; def : ARMV6Pat<(sra (bswap GPR:$Rm), (i32 16)), (REVSH GPR:$Rm)>;

4
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -2604,6 +2604,10 @@ def : T2Pat<(sext_inreg (or (srl (and rGPR:$Rm, 0xFF00), (i32 8)),
(shl rGPR:$Rm, (i32 8))), i16), (shl rGPR:$Rm, (i32 8))), i16),
(t2REVSH rGPR:$Rm)>; (t2REVSH rGPR:$Rm)>;
def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
(and (srl rGPR:$Rm, (i32 8)), 0xFF)),
(t2REVSH rGPR:$Rm)>;
def : T2Pat<(sra (bswap rGPR:$Rm), (i32 16)), (t2REVSH rGPR:$Rm)>; def : T2Pat<(sra (bswap rGPR:$Rm), (i32 16)), (t2REVSH rGPR:$Rm)>;
def t2PKHBT : T2ThreeReg< def t2PKHBT : T2ThreeReg<

13
test/CodeGen/ARM/rev.ll
View File

@ -54,3 +54,16 @@ entry:
%conv8 = ashr exact i32 %sext, 16 %conv8 = ashr exact i32 %sext, 16
ret i32 %conv8 ret i32 %conv8
} }
; rdar://9609059
define i32 @test5(i32 %i) nounwind readnone {
entry:
; CHECK: test5
; CHECK: revsh r0, r0
%shl = shl i32 %i, 24
%shr = ashr exact i32 %shl, 16
%shr23 = lshr i32 %i, 8
%and = and i32 %shr23, 255
%or = or i32 %shr, %and
ret i32 %or
}