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https://github.com/c64scene-ar/llvm-6502.git
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Implement vector constants which are splat of
integers with mov + vdup. 8003375. This is currently disabled by default because LICM will not hoist a VDUP, so it pessimizes the code if the construct occurs inside a loop (8248029). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109799 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen
parent
fb13b95162
commit
f630c712b1
@ -57,6 +57,13 @@ EnableARMTailCalls("arm-tail-calls", cl::Hidden,
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cl::desc("Generate tail calls (TEMPORARY OPTION)."),
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cl::init(true));
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// This option should go away when Machine LICM is smart enough to hoist a
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// reg-to-reg VDUP.
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static cl::opt<bool>
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EnableARMVDUPsplat("arm-vdup-splat", cl::Hidden,
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cl::desc("Generate VDUP for integer constant splats (TEMPORARY OPTION)."),
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cl::init(false));
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static cl::opt<bool>
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EnableARMLongCalls("arm-long-calls", cl::Hidden,
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cl::desc("Generate calls via indirect call instructions"),
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@ -3257,9 +3264,30 @@ static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
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return true;
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}
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// If N is an integer constant that can be moved into a register in one
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// instruction, return an SDValue of such a constant (will become a MOV
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// instruction). Otherwise return null.
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static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
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const ARMSubtarget *ST, DebugLoc dl) {
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uint64_t Val;
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if (!isa<ConstantSDNode>(N))
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return SDValue();
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Val = cast<ConstantSDNode>(N)->getZExtValue();
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if (ST->isThumb1Only()) {
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if (Val <= 255 || ~Val <= 255)
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return DAG.getConstant(Val, MVT::i32);
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} else {
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if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
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return DAG.getConstant(Val, MVT::i32);
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}
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return SDValue();
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}
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// If this is a case we can't handle, return null and let the default
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// expansion code take care of it.
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static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
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static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
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const ARMSubtarget *ST) {
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BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
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DebugLoc dl = Op.getDebugLoc();
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EVT VT = Op.getValueType();
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@ -3319,15 +3347,41 @@ static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
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if (isOnlyLowElement)
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return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
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// If all elements are constants, fall back to the default expansion, which
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// will generate a load from the constant pool.
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unsigned EltSize = VT.getVectorElementType().getSizeInBits();
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if (EnableARMVDUPsplat) {
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// Use VDUP for non-constant splats. For f32 constant splats, reduce to
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// i32 and try again.
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if (usesOnlyOneValue && EltSize <= 32) {
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if (!isConstant)
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return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
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if (VT.getVectorElementType().isFloatingPoint()) {
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SmallVector<SDValue, 8> Ops;
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for (unsigned i = 0; i < NumElts; ++i)
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Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
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Op.getOperand(i)));
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SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &Ops[0],
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NumElts);
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return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
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LowerBUILD_VECTOR(Val, DAG, ST));
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}
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SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
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if (Val.getNode())
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return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
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}
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}
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// If all elements are constants and the case above didn't get hit, fall back
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// to the default expansion, which will generate a load from the constant
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// pool.
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if (isConstant)
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return SDValue();
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// Use VDUP for non-constant splats.
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unsigned EltSize = VT.getVectorElementType().getSizeInBits();
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if (usesOnlyOneValue && EltSize <= 32)
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return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
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if (!EnableARMVDUPsplat) {
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// Use VDUP for non-constant splats.
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if (usesOnlyOneValue && EltSize <= 32)
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return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
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}
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// Vectors with 32- or 64-bit elements can be built by directly assigning
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// the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
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@ -3647,7 +3701,7 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
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case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
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case ISD::VSETCC: return LowerVSETCC(Op, DAG);
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case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
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case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
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case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
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case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
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case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
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38
test/CodeGen/Thumb2/machine-licm-vdup.ll
Normal file
38
test/CodeGen/Thumb2/machine-licm-vdup.ll
Normal file
@ -0,0 +1,38 @@
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-fp-elim -arm-vdup-splat | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim -arm-vdup-splat | FileCheck %s
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; Modified version of machine-licm.ll with -arm-vdup-splat turned on, 8003375.
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; Eventually this should become the default and be moved into machine-licm.ll.
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; FIXME: the vdup should be hoisted out of the loop, 8248029.
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define void @t2(i8* %ptr1, i8* %ptr2) nounwind {
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entry:
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; CHECK: t2:
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; CHECK: mov.w r3, #1065353216
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br i1 undef, label %bb1, label %bb2
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bb1:
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; CHECK-NEXT: %bb1
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; CHECK: vdup.32 q1, r3
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%indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %entry ]
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%tmp1 = shl i32 %indvar, 2
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%gep1 = getelementptr i8* %ptr1, i32 %tmp1
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%tmp2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %gep1)
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%tmp3 = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, <4 x float> %tmp2)
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%gep2 = getelementptr i8* %ptr2, i32 %tmp1
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call void @llvm.arm.neon.vst1.v4f32(i8* %gep2, <4 x float> %tmp3)
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%indvar.next = add i32 %indvar, 1
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%cond = icmp eq i32 %indvar.next, 10
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br i1 %cond, label %bb2, label %bb1
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bb2:
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ret void
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}
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; CHECK-NOT: LCPI1_0:
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; CHECK: .subsections_via_symbols
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declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*) nounwind readonly
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declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>) nounwind
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declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone
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